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ARM: SoC fixes for 3.4

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I will stop trying to predict when we're done with fixes for a release.
 
 Here's another small batch of three patches for arm-soc:
 
 - A fix for a boot time WARN_ON() due to irq domain conversion on PRIMA2
 - Fix for a regression in Tegra SMP spinup code due to swapped register offsets
 - Fixed config dependency for mv_cesa crypto driver to avoid build breakage
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM: SoC fixes from Olof Johansson:
 "I will stop trying to predict when we're done with fixes for a
  release.

  Here's another small batch of three patches for arm-soc:

   - A fix for a boot time WARN_ON() due to irq domain conversion on
     PRIMA2
   - Fix for a regression in Tegra SMP spinup code due to swapped
     register offsets
   - Fixed config dependency for mv_cesa crypto driver to avoid build
     breakage"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: PRIMA2: fix irq domain size and IRQ mask of internal interrupt controller
  crypto: mv_cesa requires on CRYPTO_HASH to build
  ARM: tegra: Fix flow controller accesses
This commit is contained in:
Linus Torvalds 2012-05-17 09:46:07 -07:00
commit 674ff51776
3 changed files with 7 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/mach-prima2/irq.c
View file

@ -42,7 +42,8 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
static __init void sirfsoc_irq_init(void) static __init void sirfsoc_irq_init(void)
{ {
sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32); sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
SIRFSOC_INTENAL_IRQ_END + 1 - 32);
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
@ -68,7 +69,8 @@ void __init sirfsoc_of_irq_init(void)
if (!sirfsoc_intc_base) if (!sirfsoc_intc_base)
panic("unable to map intc cpu registers\n"); panic("unable to map intc cpu registers\n");
irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL); irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
&irq_domain_simple_ops, NULL);
of_node_put(np); of_node_put(np);

4
arch/arm/mach-tegra/flowctrl.c
View file

@ -53,10 +53,10 @@ static void flowctrl_update(u8 offset, u32 value)
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{ {
return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
} }
void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
{ {
return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
} }

1
drivers/crypto/Kconfig
View file

@ -164,6 +164,7 @@ config CRYPTO_DEV_MV_CESA
select CRYPTO_ALGAPI select CRYPTO_ALGAPI
select CRYPTO_AES select CRYPTO_AES
select CRYPTO_BLKCIPHER2 select CRYPTO_BLKCIPHER2
select CRYPTO_HASH
help help
This driver allows you to utilize the Cryptographic Engines and This driver allows you to utilize the Cryptographic Engines and
Security Accelerator (CESA) which can be found on the Marvell Orion Security Accelerator (CESA) which can be found on the Marvell Orion