mirror of
https://github.com/Fishwaldo/Star64_linux.git
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media: add wave5 v4l2 driver from mail list
Signed-off-by: Som Qin <som.qin@starfivetech.com>
This commit is contained in:
Som Qin
parent
e9ae40dd4b
commit
714ddc7310
22 changed files with 11075 additions and 0 deletions
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@ -207,6 +207,8 @@ CONFIG_VIN_SENSOR_SC2235=y
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CONFIG_VIN_SENSOR_OV4689=y
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CONFIG_VIN_SENSOR_IMX219=y
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CONFIG_VIDEO_IMX708=y
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CONFIG_V4L_MEM2MEM_DRIVERS=y
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CONFIG_VIDEO_WAVE_VPU=m
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CONFIG_DRM_I2C_NXP_TDA998X=y
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CONFIG_DRM_VERISILICON=y
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CONFIG_STARFIVE_INNO_HDMI=y
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@ -253,6 +253,8 @@ config VIDEO_CODA
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Coda is a range of video codec IPs that supports
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H.264, MPEG-4, and other video formats.
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source "drivers/media/platform/chips-media/Kconfig"
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config VIDEO_IMX_VDOA
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def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST
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@ -19,6 +19,7 @@ obj-y += ti-vpe/
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obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
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obj-$(CONFIG_VIDEO_CODA) += coda/
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obj-y += chips-media/
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obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o
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obj-$(CONFIG_VIDEO_IMX8_JPEG) += imx-jpeg/
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4
drivers/media/platform/chips-media/Kconfig
Normal file
4
drivers/media/platform/chips-media/Kconfig
Normal file
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@ -0,0 +1,4 @@
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comment "Chips&Media media platform drivers"
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source "drivers/media/platform/chips-media/wave5/Kconfig"
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4
drivers/media/platform/chips-media/Makefile
Normal file
4
drivers/media/platform/chips-media/Makefile
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += wave5/
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12
drivers/media/platform/chips-media/wave5/Kconfig
Normal file
12
drivers/media/platform/chips-media/wave5/Kconfig
Normal file
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0
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config VIDEO_WAVE_VPU
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tristate "Chips&Media Wave Codec Driver"
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depends on VIDEO_DEV
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select VIDEOBUF2_DMA_CONTIG
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select VIDEOBUF2_VMALLOC
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select V4L2_MEM2MEM_DEV
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help
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Chips&Media stateful encoder and decoder driver.
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The driver supports HEVC and H264 formats.
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To compile this driver as modules, choose M here: the
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modules will be called wave5.
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10
drivers/media/platform/chips-media/wave5/Makefile
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10
drivers/media/platform/chips-media/wave5/Makefile
Normal file
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_VIDEO_WAVE_VPU) += wave5.o
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wave5-objs += wave5-hw.o \
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wave5-vpuapi.o \
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wave5-vdi.o \
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wave5-vpu-dec.o \
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wave5-vpu.o \
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wave5-vpu-enc.o \
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wave5-helper.o
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175
drivers/media/platform/chips-media/wave5/wave5-helper.c
Normal file
175
drivers/media/platform/chips-media/wave5/wave5-helper.c
Normal file
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@ -0,0 +1,175 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Wave5 series multi-standard codec IP - decoder interface
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*
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* Copyright (C) 2021 CHIPS&MEDIA INC
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*/
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#include "wave5-helper.h"
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void wave5_cleanup_instance(struct vpu_instance *inst)
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{
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int i;
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for (i = 0; i < inst->dst_buf_count; i++)
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wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]);
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wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf);
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v4l2_ctrl_handler_free(&inst->v4l2_ctrl_hdl);
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if (inst->v4l2_m2m_dev != NULL)
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v4l2_m2m_release(inst->v4l2_m2m_dev);
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if (inst->v4l2_fh.vdev != NULL) {
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v4l2_fh_del(&inst->v4l2_fh);
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v4l2_fh_exit(&inst->v4l2_fh);
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}
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list_del_init(&inst->list);
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kfifo_free(&inst->irq_status);
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ida_free(&inst->dev->inst_ida, inst->id);
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kfree(inst);
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}
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int wave5_vpu_release_device(struct file *filp,
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int (*close_func)(struct vpu_instance *inst, u32 *fail_res),
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char *name)
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{
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struct vpu_instance *inst = wave5_to_vpu_inst(filp->private_data);
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v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx);
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if (inst->state != VPU_INST_STATE_NONE) {
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u32 fail_res;
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int retry_count = 10;
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int ret;
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do {
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fail_res = 0;
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ret = close_func(inst, &fail_res);
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if (ret && ret != -EIO)
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break;
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if (fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING)
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break;
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if (!wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT))
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break;
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} while (--retry_count);
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if (fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) {
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dev_err(inst->dev->dev, "%s close failed, device is still running\n",
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name);
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return -EBUSY;
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}
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if (ret && ret != -EIO) {
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dev_err(inst->dev->dev, "%s close, fail: %d\n", name, ret);
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return ret;
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}
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}
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wave5_cleanup_instance(inst);
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return 0;
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}
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int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq,
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const struct vb2_ops *ops)
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{
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struct vpu_instance *inst = priv;
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int ret;
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src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
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src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
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src_vq->mem_ops = &vb2_dma_contig_memops;
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src_vq->ops = ops;
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src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
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src_vq->buf_struct_size = sizeof(struct vpu_buffer);
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src_vq->drv_priv = inst;
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src_vq->lock = &inst->dev->dev_lock;
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src_vq->dev = inst->dev->v4l2_dev.dev;
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ret = vb2_queue_init(src_vq);
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if (ret)
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return ret;
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dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
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dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
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dst_vq->mem_ops = &vb2_dma_contig_memops;
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dst_vq->ops = ops;
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dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
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dst_vq->buf_struct_size = sizeof(struct vpu_buffer);
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dst_vq->drv_priv = inst;
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dst_vq->lock = &inst->dev->dev_lock;
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dst_vq->dev = inst->dev->v4l2_dev.dev;
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ret = vb2_queue_init(dst_vq);
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if (ret)
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return ret;
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return 0;
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}
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int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub)
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{
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struct vpu_instance *inst = wave5_to_vpu_inst(fh);
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bool is_decoder = inst->type == VPU_INST_TYPE_DEC;
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dev_dbg(inst->dev->dev, "%s: [%s] type: %u id: %u | flags: %u\n", __func__,
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is_decoder ? "decoder" : "encoder", sub->type, sub->id, sub->flags);
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switch (sub->type) {
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case V4L2_EVENT_EOS:
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return v4l2_event_subscribe(fh, sub, 0, NULL);
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case V4L2_EVENT_SOURCE_CHANGE:
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if (is_decoder)
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return v4l2_src_change_event_subscribe(fh, sub);
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return -EINVAL;
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case V4L2_EVENT_CTRL:
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return v4l2_ctrl_subscribe_event(fh, sub);
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default:
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return -EINVAL;
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}
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}
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int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f)
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{
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struct vpu_instance *inst = wave5_to_vpu_inst(fh);
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int i;
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f->fmt.pix_mp.width = inst->src_fmt.width;
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f->fmt.pix_mp.height = inst->src_fmt.height;
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f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat;
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f->fmt.pix_mp.field = inst->src_fmt.field;
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f->fmt.pix_mp.flags = inst->src_fmt.flags;
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f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes;
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for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
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f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->src_fmt.plane_fmt[i].bytesperline;
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f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->src_fmt.plane_fmt[i].sizeimage;
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}
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f->fmt.pix_mp.colorspace = inst->colorspace;
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f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
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f->fmt.pix_mp.hsv_enc = inst->hsv_enc;
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f->fmt.pix_mp.quantization = inst->quantization;
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f->fmt.pix_mp.xfer_func = inst->xfer_func;
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return 0;
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}
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const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt,
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const struct vpu_format fmt_list[MAX_FMTS])
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{
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unsigned int index;
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for (index = 0; index < MAX_FMTS; index++) {
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if (fmt_list[index].v4l2_pix_fmt == v4l2_pix_fmt)
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return &fmt_list[index];
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}
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return NULL;
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}
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const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx,
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const struct vpu_format fmt_list[MAX_FMTS])
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{
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if (idx >= MAX_FMTS)
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return NULL;
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if (!fmt_list[idx].v4l2_pix_fmt)
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return NULL;
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return &fmt_list[idx];
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}
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28
drivers/media/platform/chips-media/wave5/wave5-helper.h
Normal file
28
drivers/media/platform/chips-media/wave5/wave5-helper.h
Normal file
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Wave5 series multi-standard codec IP - basic types
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*
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* Copyright (C) 2021 CHIPS&MEDIA INC
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*/
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#ifndef __WAVE_HELPER_H__
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#define __WAVE_HELPER_H__
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#include "wave5-vpu.h"
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#define FMT_TYPES 2
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#define MAX_FMTS 6
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void wave5_cleanup_instance(struct vpu_instance *inst);
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int wave5_vpu_release_device(struct file *filp,
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int (*close_func)(struct vpu_instance *inst, u32 *fail_res),
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char *name);
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int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq,
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const struct vb2_ops *ops);
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int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub);
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int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f);
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const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt,
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const struct vpu_format fmt_list[MAX_FMTS]);
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const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx,
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const struct vpu_format fmt_list[MAX_FMTS]);
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#endif
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3359
drivers/media/platform/chips-media/wave5/wave5-hw.c
Normal file
3359
drivers/media/platform/chips-media/wave5/wave5-hw.c
Normal file
File diff suppressed because it is too large
Load diff
743
drivers/media/platform/chips-media/wave5/wave5-regdefine.h
Normal file
743
drivers/media/platform/chips-media/wave5/wave5-regdefine.h
Normal file
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@ -0,0 +1,743 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Wave5 series multi-standard codec IP - wave5 register definitions
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*
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* Copyright (C) 2021 CHIPS&MEDIA INC
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*/
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#ifndef __WAVE5_REGISTER_DEFINE_H__
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#define __WAVE5_REGISTER_DEFINE_H__
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enum W5_VPU_COMMAND {
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W5_INIT_VPU = 0x0001,
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W5_WAKEUP_VPU = 0x0002,
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W5_SLEEP_VPU = 0x0004,
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W5_CREATE_INSTANCE = 0x0008, /* queuing command */
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W5_FLUSH_INSTANCE = 0x0010,
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W5_DESTROY_INSTANCE = 0x0020, /* queuing command */
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W5_INIT_SEQ = 0x0040, /* queuing command */
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W5_SET_FB = 0x0080,
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W5_DEC_PIC = 0x0100, /* queuing command */
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W5_ENC_PIC = 0x0100, /* queuing command */
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W5_ENC_SET_PARAM = 0x0200, /* queuing command */
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W5_QUERY = 0x4000,
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W5_UPDATE_BS = 0x8000,
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W5_MAX_VPU_COMD = 0x10000,
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};
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enum QUERY_OPT {
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GET_VPU_INFO = 0,
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SET_WRITE_PROT = 1,
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GET_RESULT = 2,
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UPDATE_DISP_FLAG = 3,
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GET_BW_REPORT = 4,
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GET_BS_RD_PTR = 5, // for decoder
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GET_BS_WR_PTR = 6, // for encoder
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GET_SRC_BUF_FLAG = 7, // for encoder
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SET_BS_RD_PTR = 8, // for decoder
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GET_DEBUG_INFO = 0x61,
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};
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/*
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* A flag of user data buffer full.
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* User data buffer full flag equal to 1 specifies that de-
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* coded frame has more user data size than VPU internal
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* buffer. VPU only dumps the internal buffer size of us-
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* er data to USER_DATA_BUF_BASE buffer. In other
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* words, VPU is unable to report the rest of the user data to
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* USER_DATA_BUF_BASE buffer after the internal buffer
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* fullness happens.
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*/
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#define USERDATA_FLAG_BUFF_FULL 1
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#define W5_REG_BASE 0x00000000
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#define W5_CMD_REG_BASE 0x00000100
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#define W5_CMD_REG_END 0x00000200
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/*
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* common
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*/
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/* power on configuration
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* PO_DEBUG_MODE [0] 1 - power on with debug mode
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* USE_PO_CONF [3] 1 - use power-on-configuration
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*/
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#define W5_PO_CONF (W5_REG_BASE + 0x0000)
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#define W5_VCPU_CUR_PC (W5_REG_BASE + 0x0004)
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#define W5_VCPU_CUR_LR (W5_REG_BASE + 0x0008)
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#define W5_VPU_PDBG_STEP_MASK_V (W5_REG_BASE + 0x000C)
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#define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) // v_cpu debugger ctrl register
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#define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) // v_cpu debugger index register
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#define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) // v_cpu debugger write data register
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#define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) // v_cpu debugger read data register
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#define W5_VPU_FIO_CTRL_ADDR (W5_REG_BASE + 0x0020)
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#define W5_VPU_FIO_DATA (W5_REG_BASE + 0x0024)
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#define W5_VPU_VINT_REASON_USR (W5_REG_BASE + 0x0030)
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#define W5_VPU_VINT_REASON_CLR (W5_REG_BASE + 0x0034)
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#define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
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#define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
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#define W5_VPU_HINT_CLEAR (W5_REG_BASE + 0x0040)
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#define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
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#define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
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#define W5_VPU_VINT_REASON (W5_REG_BASE + 0x004C)
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#define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
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#define W5_RST_BLOCK_CCLK(_core) BIT((_core))
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#define W5_RST_BLOCK_CCLK_ALL (0xff)
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#define W5_RST_BLOCK_BCLK(_core) (0x100 << (_core))
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#define W5_RST_BLOCK_BCLK_ALL (0xff00)
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#define W5_RST_BLOCK_ACLK(_core) (0x10000 << (_core))
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#define W5_RST_BLOCK_ACLK_ALL (0xff0000)
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#define W5_RST_BLOCK_VCPU_ALL (0x3f000000)
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#define W5_RST_BLOCK_ALL (0x3fffffff)
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#define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
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#define W5_VCPU_RESTART (W5_REG_BASE + 0x0058)
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#define W5_VPU_CLK_MASK (W5_REG_BASE + 0x005C)
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/* REMAP_CTRL
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* PAGE SIZE: [8:0] 0x001 - 4K
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* 0x002 - 8K
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* 0x004 - 16K
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* ...
|
||||
* 0x100 - 1M
|
||||
* REGION ATTR1 [10] 0 - normal
|
||||
* 1 - make bus error for the region
|
||||
* REGION ATTR2 [11] 0 - normal
|
||||
* 1 - bypass region
|
||||
* REMAP INDEX [15:12] - 0 ~ 3
|
||||
* ENDIAN [19:16] - see endian_mode in vdi.h
|
||||
* AXI-ID [23:20] - upper AXI-ID
|
||||
* BUS_ERROR [29] 0 - bypass
|
||||
* 1 - make BUS_ERROR for unmapped region
|
||||
* BYPASS_ALL [30] 1 - bypass all
|
||||
* ENABLE [31] 1 - update control register[30:16]
|
||||
*/
|
||||
#define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
|
||||
#define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
|
||||
#define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
|
||||
#define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
|
||||
#define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
|
||||
#define W5_VPU_HALT_STATUS (W5_REG_BASE + 0x0074)
|
||||
#define W5_VPU_VCPU_STATUS (W5_REG_BASE + 0x0078)
|
||||
#define W5_VPU_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0094)
|
||||
/*
|
||||
* assign vpu_config0 = {conf_map_converter_reg, // [31]
|
||||
* conf_map_converter_sig, // [30]
|
||||
* 8'd0, // [29:22]
|
||||
* conf_std_switch_en, // [21]
|
||||
* conf_bg_detect, // [20]
|
||||
* conf_3dnr_en, // [19]
|
||||
* conf_one_axi_en, // [18]
|
||||
* conf_sec_axi_en, // [17]
|
||||
* conf_bus_info, // [16]
|
||||
* conf_afbc_en, // [15]
|
||||
* conf_afbc_version_id, // [14:12]
|
||||
* conf_fbc_en, // [11]
|
||||
* conf_fbc_version_id, // [10:08]
|
||||
* conf_scaler_en, // [07]
|
||||
* conf_scaler_version_id, // [06:04]
|
||||
* conf_bwb_en, // [03]
|
||||
* 3'd0}; // [02:00]
|
||||
*/
|
||||
#define W5_VPU_RET_VPU_CONFIG0 (W5_REG_BASE + 0x0098)
|
||||
/*
|
||||
* assign vpu_config1 = {4'd0, // [31:28]
|
||||
* conf_perf_timer_en, // [27]
|
||||
* conf_multi_core_en, // [26]
|
||||
* conf_gcu_en, // [25]
|
||||
* conf_cu_report, // [24]
|
||||
* 4'd0, // [23:20]
|
||||
* conf_vcore_id_3, // [19]
|
||||
* conf_vcore_id_2, // [18]
|
||||
* conf_vcore_id_1, // [17]
|
||||
* conf_vcore_id_0, // [16]
|
||||
* conf_bwb_opt, // [15]
|
||||
* 7'd0, // [14:08]
|
||||
* conf_cod_std_en_reserved_7, // [7]
|
||||
* conf_cod_std_en_reserved_6, // [6]
|
||||
* conf_cod_std_en_reserved_5, // [5]
|
||||
* conf_cod_std_en_reserved_4, // [4]
|
||||
* conf_cod_std_en_reserved_3, // [3]
|
||||
* conf_cod_std_en_reserved_2, // [2]
|
||||
* conf_cod_std_en_vp9, // [1]
|
||||
* conf_cod_std_en_hevc}; // [0]
|
||||
* }
|
||||
*/
|
||||
#define W5_VPU_RET_VPU_CONFIG1 (W5_REG_BASE + 0x009C)
|
||||
|
||||
#define W5_VPU_DBG_REG0 (W5_REG_BASE + 0x00f0)
|
||||
#define W5_VPU_DBG_REG1 (W5_REG_BASE + 0x00f4)
|
||||
#define W5_VPU_DBG_REG2 (W5_REG_BASE + 0x00f8)
|
||||
#define W5_VPU_DBG_REG3 (W5_REG_BASE + 0x00fc)
|
||||
|
||||
/************************************************************************/
|
||||
/* PRODUCT INFORMATION */
|
||||
/************************************************************************/
|
||||
#define W5_PRODUCT_NAME (W5_REG_BASE + 0x1040)
|
||||
#define W5_PRODUCT_NUMBER (W5_REG_BASE + 0x1044)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER/ENCODER COMMON */
|
||||
/************************************************************************/
|
||||
#define W5_COMMAND (W5_REG_BASE + 0x0100)
|
||||
#define W5_COMMAND_OPTION (W5_REG_BASE + 0x0104)
|
||||
#define W5_QUERY_OPTION (W5_REG_BASE + 0x0104)
|
||||
#define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
|
||||
#define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
|
||||
#define W5_RET_QUEUE_FAIL_REASON (W5_REG_BASE + 0x0110)
|
||||
#define W5_CMD_INSTANCE_INFO (W5_REG_BASE + 0x0110)
|
||||
|
||||
#define W5_RET_QUEUE_STATUS (W5_REG_BASE + 0x01E0)
|
||||
#define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
|
||||
#define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
|
||||
#define W5_RET_STAGE0_INSTANCE_INFO (W5_REG_BASE + 0x01EC)
|
||||
#define W5_RET_STAGE1_INSTANCE_INFO (W5_REG_BASE + 0x01F0)
|
||||
#define W5_RET_STAGE2_INSTANCE_INFO (W5_REG_BASE + 0x01F4)
|
||||
|
||||
#define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
|
||||
|
||||
#define W5_BS_OPTION (W5_REG_BASE + 0x0120)
|
||||
|
||||
// return info when QUERY (GET_RESULT) for en/decoder
|
||||
#define W5_RET_VLC_BUF_SIZE (W5_REG_BASE + 0x01B0)
|
||||
// return info when QUERY (GET_RESULT) for en/decoder
|
||||
#define W5_RET_PARAM_BUF_SIZE (W5_REG_BASE + 0x01B4)
|
||||
|
||||
// set when SET_FB for en/decoder
|
||||
#define W5_CMD_SET_FB_ADDR_TASK_BUF (W5_REG_BASE + 0x01D4)
|
||||
#define W5_CMD_SET_FB_TASK_BUF_SIZE (W5_REG_BASE + 0x01D8)
|
||||
/************************************************************************/
|
||||
/* INIT_VPU - COMMON */
|
||||
/************************************************************************/
|
||||
/* note: W5_ADDR_CODE_BASE should be aligned to 4KB */
|
||||
#define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
|
||||
#define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
|
||||
#define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
|
||||
#define W5_ADDR_TEMP_BASE (W5_REG_BASE + 0x011C)
|
||||
#define W5_TEMP_SIZE (W5_REG_BASE + 0x0120)
|
||||
#define W5_ADDR_SEC_AXI (W5_REG_BASE + 0x0124)
|
||||
#define W5_SEC_AXI_SIZE (W5_REG_BASE + 0x0128)
|
||||
#define W5_HW_OPTION (W5_REG_BASE + 0x012C)
|
||||
#define W5_SEC_AXI_PARAM (W5_REG_BASE + 0x0180)
|
||||
|
||||
/************************************************************************/
|
||||
/* CREATE_INSTANCE - COMMON */
|
||||
/************************************************************************/
|
||||
#define W5_ADDR_WORK_BASE (W5_REG_BASE + 0x0114)
|
||||
#define W5_WORK_SIZE (W5_REG_BASE + 0x0118)
|
||||
#define W5_CMD_DEC_BS_START_ADDR (W5_REG_BASE + 0x011C)
|
||||
#define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120)
|
||||
#define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124)
|
||||
#define W5_CMD_EXT_ADDR (W5_REG_BASE + 0x0138)
|
||||
#define W5_CMD_NUM_CQ_DEPTH_M1 (W5_REG_BASE + 0x013C)
|
||||
#define W5_CMD_ERR_CONCEAL (W5_REG_BASE + 0x0140)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - INIT_SEQ */
|
||||
/************************************************************************/
|
||||
#define W5_BS_RD_PTR (W5_REG_BASE + 0x0118)
|
||||
#define W5_BS_WR_PTR (W5_REG_BASE + 0x011C)
|
||||
/************************************************************************/
|
||||
/* SET_FRAME_BUF */
|
||||
/************************************************************************/
|
||||
/* SET_FB_OPTION 0x00 REGISTER FRAMEBUFFERS
|
||||
* 0x01 UPDATE FRAMEBUFFER, just one framebuffer(linear, fbc and mvcol)
|
||||
*/
|
||||
#define W5_SFB_OPTION (W5_REG_BASE + 0x0104)
|
||||
#define W5_COMMON_PIC_INFO (W5_REG_BASE + 0x0118)
|
||||
#define W5_PIC_SIZE (W5_REG_BASE + 0x011C)
|
||||
#define W5_SET_FB_NUM (W5_REG_BASE + 0x0120)
|
||||
#define W5_EXTRA_PIC_INFO (W5_REG_BASE + 0x0124)
|
||||
|
||||
#define W5_ADDR_LUMA_BASE0 (W5_REG_BASE + 0x0134)
|
||||
#define W5_ADDR_CB_BASE0 (W5_REG_BASE + 0x0138)
|
||||
#define W5_ADDR_CR_BASE0 (W5_REG_BASE + 0x013C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET0 (W5_REG_BASE + 0x013C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET0 (W5_REG_BASE + 0x0140)
|
||||
#define W5_ADDR_LUMA_BASE1 (W5_REG_BASE + 0x0144)
|
||||
#define W5_ADDR_CB_ADDR1 (W5_REG_BASE + 0x0148)
|
||||
#define W5_ADDR_CR_ADDR1 (W5_REG_BASE + 0x014C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET1 (W5_REG_BASE + 0x014C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET1 (W5_REG_BASE + 0x0150)
|
||||
#define W5_ADDR_LUMA_BASE2 (W5_REG_BASE + 0x0154)
|
||||
#define W5_ADDR_CB_ADDR2 (W5_REG_BASE + 0x0158)
|
||||
#define W5_ADDR_CR_ADDR2 (W5_REG_BASE + 0x015C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET2 (W5_REG_BASE + 0x015C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET2 (W5_REG_BASE + 0x0160)
|
||||
#define W5_ADDR_LUMA_BASE3 (W5_REG_BASE + 0x0164)
|
||||
#define W5_ADDR_CB_ADDR3 (W5_REG_BASE + 0x0168)
|
||||
#define W5_ADDR_CR_ADDR3 (W5_REG_BASE + 0x016C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET3 (W5_REG_BASE + 0x016C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET3 (W5_REG_BASE + 0x0170)
|
||||
#define W5_ADDR_LUMA_BASE4 (W5_REG_BASE + 0x0174)
|
||||
#define W5_ADDR_CB_ADDR4 (W5_REG_BASE + 0x0178)
|
||||
#define W5_ADDR_CR_ADDR4 (W5_REG_BASE + 0x017C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET4 (W5_REG_BASE + 0x017C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET4 (W5_REG_BASE + 0x0180)
|
||||
#define W5_ADDR_LUMA_BASE5 (W5_REG_BASE + 0x0184)
|
||||
#define W5_ADDR_CB_ADDR5 (W5_REG_BASE + 0x0188)
|
||||
#define W5_ADDR_CR_ADDR5 (W5_REG_BASE + 0x018C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET5 (W5_REG_BASE + 0x018C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET5 (W5_REG_BASE + 0x0190)
|
||||
#define W5_ADDR_LUMA_BASE6 (W5_REG_BASE + 0x0194)
|
||||
#define W5_ADDR_CB_ADDR6 (W5_REG_BASE + 0x0198)
|
||||
#define W5_ADDR_CR_ADDR6 (W5_REG_BASE + 0x019C)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET6 (W5_REG_BASE + 0x019C)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET6 (W5_REG_BASE + 0x01A0)
|
||||
#define W5_ADDR_LUMA_BASE7 (W5_REG_BASE + 0x01A4)
|
||||
#define W5_ADDR_CB_ADDR7 (W5_REG_BASE + 0x01A8)
|
||||
#define W5_ADDR_CR_ADDR7 (W5_REG_BASE + 0x01AC)
|
||||
// compression offset table for luma
|
||||
#define W5_ADDR_FBC_Y_OFFSET7 (W5_REG_BASE + 0x01AC)
|
||||
// compression offset table for chroma
|
||||
#define W5_ADDR_FBC_C_OFFSET7 (W5_REG_BASE + 0x01B0)
|
||||
#define W5_ADDR_MV_COL0 (W5_REG_BASE + 0x01B4)
|
||||
#define W5_ADDR_MV_COL1 (W5_REG_BASE + 0x01B8)
|
||||
#define W5_ADDR_MV_COL2 (W5_REG_BASE + 0x01BC)
|
||||
#define W5_ADDR_MV_COL3 (W5_REG_BASE + 0x01C0)
|
||||
#define W5_ADDR_MV_COL4 (W5_REG_BASE + 0x01C4)
|
||||
#define W5_ADDR_MV_COL5 (W5_REG_BASE + 0x01C8)
|
||||
#define W5_ADDR_MV_COL6 (W5_REG_BASE + 0x01CC)
|
||||
#define W5_ADDR_MV_COL7 (W5_REG_BASE + 0x01D0)
|
||||
|
||||
/* UPDATE_FB */
|
||||
/* CMD_SET_FB_STRIDE [15:0] - FBC framebuffer stride
|
||||
* [31:15] - linear framebuffer stride
|
||||
*/
|
||||
#define W5_CMD_SET_FB_STRIDE (W5_REG_BASE + 0x0118)
|
||||
#define W5_CMD_SET_FB_INDEX (W5_REG_BASE + 0x0120)
|
||||
#define W5_ADDR_LUMA_BASE (W5_REG_BASE + 0x0134)
|
||||
#define W5_ADDR_CB_BASE (W5_REG_BASE + 0x0138)
|
||||
#define W5_ADDR_CR_BASE (W5_REG_BASE + 0x013C)
|
||||
#define W5_ADDR_MV_COL (W5_REG_BASE + 0x0140)
|
||||
#define W5_ADDR_FBC_Y_BASE (W5_REG_BASE + 0x0144)
|
||||
#define W5_ADDR_FBC_C_BASE (W5_REG_BASE + 0x0148)
|
||||
#define W5_ADDR_FBC_Y_OFFSET (W5_REG_BASE + 0x014C)
|
||||
#define W5_ADDR_FBC_C_OFFSET (W5_REG_BASE + 0x0150)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - DEC_PIC */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_DEC_VCORE_INFO (W5_REG_BASE + 0x0194)
|
||||
/* sequence change enable mask register
|
||||
* CMD_SEQ_CHANGE_ENABLE_FLAG [5] profile_idc
|
||||
* [16] pic_width/height_in_luma_sample
|
||||
* [19] sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase
|
||||
*/
|
||||
#define W5_CMD_SEQ_CHANGE_ENABLE_FLAG (W5_REG_BASE + 0x0128)
|
||||
#define W5_CMD_DEC_USER_MASK (W5_REG_BASE + 0x012C)
|
||||
#define W5_CMD_DEC_TEMPORAL_ID_PLUS1 (W5_REG_BASE + 0x0130)
|
||||
#define W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (W5_REG_BASE + 0x0134)
|
||||
#define W5_USE_SEC_AXI (W5_REG_BASE + 0x0150)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - QUERY : GET_VPU_INFO */
|
||||
/************************************************************************/
|
||||
#define W5_RET_FW_VERSION (W5_REG_BASE + 0x0118)
|
||||
#define W5_RET_PRODUCT_NAME (W5_REG_BASE + 0x011C)
|
||||
#define W5_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0120)
|
||||
#define W5_RET_STD_DEF0 (W5_REG_BASE + 0x0124)
|
||||
#define W5_RET_STD_DEF1 (W5_REG_BASE + 0x0128)
|
||||
#define W5_RET_CONF_FEATURE (W5_REG_BASE + 0x012C)
|
||||
#define W5_RET_CONF_DATE (W5_REG_BASE + 0x0130)
|
||||
#define W5_RET_CONF_REVISION (W5_REG_BASE + 0x0134)
|
||||
#define W5_RET_CONF_TYPE (W5_REG_BASE + 0x0138)
|
||||
#define W5_RET_PRODUCT_ID (W5_REG_BASE + 0x013C)
|
||||
#define W5_RET_CUSTOMER_ID (W5_REG_BASE + 0x0140)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - QUERY : GET_RESULT */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_DEC_ADDR_REPORT_BASE (W5_REG_BASE + 0x0114)
|
||||
#define W5_CMD_DEC_REPORT_SIZE (W5_REG_BASE + 0x0118)
|
||||
#define W5_CMD_DEC_REPORT_PARAM (W5_REG_BASE + 0x011C)
|
||||
|
||||
#define W5_RET_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C)
|
||||
#define W5_RET_DEC_SEQ_PARAM (W5_REG_BASE + 0x0120)
|
||||
#define W5_RET_DEC_COLOR_SAMPLE_INFO (W5_REG_BASE + 0x0124)
|
||||
#define W5_RET_DEC_ASPECT_RATIO (W5_REG_BASE + 0x0128)
|
||||
#define W5_RET_DEC_BIT_RATE (W5_REG_BASE + 0x012C)
|
||||
#define W5_RET_DEC_FRAME_RATE_NR (W5_REG_BASE + 0x0130)
|
||||
#define W5_RET_DEC_FRAME_RATE_DR (W5_REG_BASE + 0x0134)
|
||||
#define W5_RET_DEC_NUM_REQUIRED_FB (W5_REG_BASE + 0x0138)
|
||||
#define W5_RET_DEC_NUM_REORDER_DELAY (W5_REG_BASE + 0x013C)
|
||||
#define W5_RET_DEC_SUB_LAYER_INFO (W5_REG_BASE + 0x0140)
|
||||
#define W5_RET_DEC_NOTIFICATION (W5_REG_BASE + 0x0144)
|
||||
/*
|
||||
* USER_DATA_FLAGS for HEVC/H264 only.
|
||||
* Bits:
|
||||
* [1] - User data buffer full boolean
|
||||
* [2] - VUI parameter flag
|
||||
* [4] - Pic_timing SEI flag
|
||||
* [5] - 1st user_data_registed_itu_t_t35 prefix SEI flag
|
||||
* [6] - user_data_unregistered prefix SEI flag
|
||||
* [7] - 1st user_data_registed_itu_t_t35 suffix SEI flag
|
||||
* [8] - user_data_unregistered suffix SEI flag
|
||||
* [10]- mastering_display_color_volume prefix SEI flag
|
||||
* [11]- chroma_resampling_display_color_volume prefix SEI flag
|
||||
* [12]- knee_function_info SEI flag
|
||||
* [13]- tone_mapping_info prefix SEI flag
|
||||
* [14]- film_grain_characteristics_info prefix SEI flag
|
||||
* [15]- content_light_level_info prefix SEI flag
|
||||
* [16]- color_remapping_info prefix SEI flag
|
||||
* [28]- 2nd user_data_registed_itu_t_t35 prefix SEI flag
|
||||
* [29]- 3rd user_data_registed_itu_t_t35 prefix SEI flag
|
||||
* [30]- 2nd user_data_registed_itu_t_t35 suffix SEI flag
|
||||
* [31]- 3rd user_data_registed_itu_t_t35 suffix SEI flag
|
||||
*/
|
||||
#define W5_RET_DEC_USERDATA_IDC (W5_REG_BASE + 0x0148)
|
||||
#define W5_RET_DEC_PIC_SIZE (W5_REG_BASE + 0x014C)
|
||||
#define W5_RET_DEC_CROP_TOP_BOTTOM (W5_REG_BASE + 0x0150)
|
||||
#define W5_RET_DEC_CROP_LEFT_RIGHT (W5_REG_BASE + 0x0154)
|
||||
/*
|
||||
* #define W5_RET_DEC_AU_START_POS (W5_REG_BASE + 0x0158)
|
||||
* => Access unit (AU) Bitstream start position
|
||||
* #define W5_RET_DEC_AU_END_POS (W5_REG_BASE + 0x015C)
|
||||
* => Access unit (AU) Bitstream end position
|
||||
*/
|
||||
|
||||
/*
|
||||
* Decoded picture type:
|
||||
* reg_val & 0x7 => picture type
|
||||
* (reg_val >> 4) & 0x3f => VCL NAL unit type
|
||||
* (reg_val >> 31) & 0x1 => output_flag
|
||||
* 16 << ((reg_val >> 10) & 0x3) => ctu_size
|
||||
*/
|
||||
#define W5_RET_DEC_PIC_TYPE (W5_REG_BASE + 0x0160)
|
||||
#define W5_RET_DEC_PIC_POC (W5_REG_BASE + 0x0164)
|
||||
/*
|
||||
* #define W5_RET_DEC_RECOVERY_POINT (W5_REG_BASE + 0x0168)
|
||||
* => HEVC recovery point
|
||||
* reg_val & 0xff => number of signed recovery picture order counts
|
||||
* (reg_val >> 16) & 0x1 => exact match flag
|
||||
* (reg_val >> 17) & 0x1 => broken link flag
|
||||
* (reg_val >> 18) & 0x1 => exist flag
|
||||
*/
|
||||
#define W5_RET_DEC_DEBUG_INDEX (W5_REG_BASE + 0x016C)
|
||||
#define W5_RET_DEC_DECODED_INDEX (W5_REG_BASE + 0x0170)
|
||||
#define W5_RET_DEC_DISPLAY_INDEX (W5_REG_BASE + 0x0174)
|
||||
/*
|
||||
* #define W5_RET_DEC_REALLOC_INDEX (W5_REG_BASE + 0x0178)
|
||||
* => display picture index in decoded picture buffer
|
||||
* reg_val & 0xf => display picture index for FBC buffer (by reordering)
|
||||
*/
|
||||
#define W5_RET_DEC_DISP_IDC (W5_REG_BASE + 0x017C)
|
||||
/*
|
||||
* #define W5_RET_DEC_ERR_CTB_NUM (W5_REG_BASE + 0x0180)
|
||||
* => Number of error CTUs
|
||||
* reg_val >> 16 => erroneous CTUs in bitstream
|
||||
* reg_val & 0xffff => total CTUs in bitstream
|
||||
*
|
||||
* #define W5_RET_DEC_PIC_PARAM (W5_REG_BASE + 0x01A0)
|
||||
* => Bitstream sequence/picture parameter information (AV1 only)
|
||||
* reg_val & 0x1 => intrabc tool enable
|
||||
* (reg_val >> 1) & 0x1 => screen content tools enable
|
||||
*/
|
||||
#define W5_RET_DEC_HOST_CMD_TICK (W5_REG_BASE + 0x01B8)
|
||||
/*
|
||||
* #define W5_RET_DEC_SEEK_START_TICK (W5_REG_BASE + 0x01BC)
|
||||
* #define W5_RET_DEC_SEEK_END_TICK (W5_REG_BASE + 0x01C0)
|
||||
* => Start and end ticks for seeking slices of the picture
|
||||
* #define W5_RET_DEC_PARSING_START_TICK (W5_REG_BASE + 0x01C4)
|
||||
* #define W5_RET_DEC_PARSING_END_TICK (W5_REG_BASE + 0x01C8)
|
||||
* => Start and end ticks for parsing slices of the picture
|
||||
* #define W5_RET_DEC_DECODING_START_TICK (W5_REG_BASE + 0x01CC)
|
||||
* => Start tick for decoding slices of the picture
|
||||
*/
|
||||
#define W5_RET_DEC_DECODING_ENC_TICK (W5_REG_BASE + 0x01D0)
|
||||
#define W5_RET_DEC_WARN_INFO (W5_REG_BASE + 0x01D4)
|
||||
#define W5_RET_DEC_ERR_INFO (W5_REG_BASE + 0x01D8)
|
||||
#define W5_RET_DEC_DECODING_SUCCESS (W5_REG_BASE + 0x01DC)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - FLUSH_INSTANCE */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_FLUSH_INST_OPT (W5_REG_BASE + 0x104)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - QUERY : UPDATE_DISP_FLAG */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_DEC_SET_DISP_IDC (W5_REG_BASE + 0x0118)
|
||||
#define W5_CMD_DEC_CLR_DISP_IDC (W5_REG_BASE + 0x011C)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - QUERY : SET_BS_RD_PTR */
|
||||
/************************************************************************/
|
||||
#define W5_RET_QUERY_DEC_SET_BS_RD_PTR (W5_REG_BASE + 0x011C)
|
||||
|
||||
/************************************************************************/
|
||||
/* DECODER - QUERY : GET_BS_RD_PTR */
|
||||
/************************************************************************/
|
||||
#define W5_RET_QUERY_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C)
|
||||
|
||||
/************************************************************************/
|
||||
/* QUERY : GET_DEBUG_INFO */
|
||||
/************************************************************************/
|
||||
#define W5_RET_QUERY_DEBUG_PRI_REASON (W5_REG_BASE + 0x114)
|
||||
|
||||
/************************************************************************/
|
||||
/* GDI register for debugging */
|
||||
/************************************************************************/
|
||||
#define W5_GDI_BASE 0x8800
|
||||
#define W5_GDI_BUS_CTRL (W5_GDI_BASE + 0x0F0)
|
||||
#define W5_GDI_BUS_STATUS (W5_GDI_BASE + 0x0F4)
|
||||
|
||||
#define W5_BACKBONE_BASE_VCPU 0xFE00
|
||||
#define W5_BACKBONE_BUS_CTRL_VCPU (W5_BACKBONE_BASE_VCPU + 0x010)
|
||||
#define W5_BACKBONE_BUS_STATUS_VCPU (W5_BACKBONE_BASE_VCPU + 0x014)
|
||||
#define W5_BACKBONE_PROG_AXI_ID (W5_BACKBONE_BASE_VCPU + 0x00C)
|
||||
|
||||
#define W5_BACKBONE_PROC_EXT_ADDR (W5_BACKBONE_BASE_VCPU + 0x0C0)
|
||||
#define W5_BACKBONE_AXI_PARAM (W5_BACKBONE_BASE_VCPU + 0x0E0)
|
||||
|
||||
#define W5_BACKBONE_BASE_VCORE0 0x8E00
|
||||
#define W5_BACKBONE_BUS_CTRL_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x010)
|
||||
#define W5_BACKBONE_BUS_STATUS_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x014)
|
||||
|
||||
#define W5_BACKBONE_BASE_VCORE1 0x9E00 // for dual-core product
|
||||
#define W5_BACKBONE_BUS_CTRL_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x010)
|
||||
#define W5_BACKBONE_BUS_STATUS_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x014)
|
||||
|
||||
#define W5_COMBINED_BACKBONE_BASE 0xFE00
|
||||
#define W5_COMBINED_BACKBONE_BUS_CTRL (W5_COMBINED_BACKBONE_BASE + 0x010)
|
||||
#define W5_COMBINED_BACKBONE_BUS_STATUS (W5_COMBINED_BACKBONE_BASE + 0x014)
|
||||
|
||||
/************************************************************************/
|
||||
/* */
|
||||
/* for ENCODER */
|
||||
/* */
|
||||
/************************************************************************/
|
||||
#define W5_RET_STAGE3_INSTANCE_INFO (W5_REG_BASE + 0x1F8)
|
||||
/************************************************************************/
|
||||
/* ENCODER - CREATE_INSTANCE */
|
||||
/************************************************************************/
|
||||
// 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON)
|
||||
#define W5_CMD_ENC_VCORE_INFO (W5_REG_BASE + 0x0194)
|
||||
#define W5_CMD_ENC_SRC_OPTIONS (W5_REG_BASE + 0x0128)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - SET_FB */
|
||||
/************************************************************************/
|
||||
#define W5_FBC_STRIDE (W5_REG_BASE + 0x128)
|
||||
#define W5_ADDR_SUB_SAMPLED_FB_BASE (W5_REG_BASE + 0x12C)
|
||||
#define W5_SUB_SAMPLED_ONE_FB_SIZE (W5_REG_BASE + 0x130)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - ENC_SET_PARAM (COMMON & CHANGE_PARAM) */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_ENC_SEQ_SET_PARAM_OPTION (W5_REG_BASE + 0x104)
|
||||
#define W5_CMD_ENC_SEQ_SET_PARAM_ENABLE (W5_REG_BASE + 0x118)
|
||||
#define W5_CMD_ENC_SEQ_SRC_SIZE (W5_REG_BASE + 0x11C)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN (W5_REG_BASE + 0x120)
|
||||
#define W5_CMD_ENC_SEQ_SPS_PARAM (W5_REG_BASE + 0x124)
|
||||
#define W5_CMD_ENC_SEQ_PPS_PARAM (W5_REG_BASE + 0x128)
|
||||
#define W5_CMD_ENC_SEQ_GOP_PARAM (W5_REG_BASE + 0x12C)
|
||||
#define W5_CMD_ENC_SEQ_INTRA_PARAM (W5_REG_BASE + 0x130)
|
||||
#define W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT (W5_REG_BASE + 0x134)
|
||||
#define W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT (W5_REG_BASE + 0x138)
|
||||
#define W5_CMD_ENC_SEQ_RDO_PARAM (W5_REG_BASE + 0x13C)
|
||||
#define W5_CMD_ENC_SEQ_INDEPENDENT_SLICE (W5_REG_BASE + 0x140)
|
||||
#define W5_CMD_ENC_SEQ_DEPENDENT_SLICE (W5_REG_BASE + 0x144)
|
||||
#define W5_CMD_ENC_SEQ_INTRA_REFRESH (W5_REG_BASE + 0x148)
|
||||
#define W5_CMD_ENC_SEQ_INPUT_SRC_PARAM (W5_REG_BASE + 0x14C)
|
||||
|
||||
#define W5_CMD_ENC_SEQ_RC_FRAME_RATE (W5_REG_BASE + 0x150)
|
||||
#define W5_CMD_ENC_SEQ_RC_TARGET_RATE (W5_REG_BASE + 0x154)
|
||||
#define W5_CMD_ENC_SEQ_RC_PARAM (W5_REG_BASE + 0x158)
|
||||
#define W5_CMD_ENC_SEQ_RC_MIN_MAX_QP (W5_REG_BASE + 0x15C)
|
||||
#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3 (W5_REG_BASE + 0x160)
|
||||
#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7 (W5_REG_BASE + 0x164)
|
||||
#define W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP (W5_REG_BASE + 0x168)
|
||||
#define W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM (W5_REG_BASE + 0x16C)
|
||||
|
||||
#define W5_CMD_ENC_SEQ_ROT_PARAM (W5_REG_BASE + 0x170)
|
||||
#define W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK (W5_REG_BASE + 0x174)
|
||||
#define W5_CMD_ENC_SEQ_TIME_SCALE (W5_REG_BASE + 0x178)
|
||||
#define W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE (W5_REG_BASE + 0x17C)
|
||||
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU04 (W5_REG_BASE + 0x184)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU08 (W5_REG_BASE + 0x188)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU16 (W5_REG_BASE + 0x18C)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU32 (W5_REG_BASE + 0x190)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU08 (W5_REG_BASE + 0x194)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU16 (W5_REG_BASE + 0x198)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU32 (W5_REG_BASE + 0x19C)
|
||||
#define W5_CMD_ENC_SEQ_NR_PARAM (W5_REG_BASE + 0x1A0)
|
||||
#define W5_CMD_ENC_SEQ_NR_WEIGHT (W5_REG_BASE + 0x1A4)
|
||||
#define W5_CMD_ENC_SEQ_BG_PARAM (W5_REG_BASE + 0x1A8)
|
||||
#define W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR (W5_REG_BASE + 0x1AC)
|
||||
#define W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR (W5_REG_BASE + 0x1B0)
|
||||
#define W5_CMD_ENC_SEQ_VUI_HRD_PARAM (W5_REG_BASE + 0x180)
|
||||
#define W5_CMD_ENC_SEQ_VUI_RBSP_ADDR (W5_REG_BASE + 0x1B8)
|
||||
#define W5_CMD_ENC_SEQ_HRD_RBSP_ADDR (W5_REG_BASE + 0x1BC)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - ENC_SET_PARAM (CUSTOM_GOP) */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PARAM (W5_REG_BASE + 0x11C)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 (W5_REG_BASE + 0x120)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1 (W5_REG_BASE + 0x124)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2 (W5_REG_BASE + 0x128)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3 (W5_REG_BASE + 0x12C)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4 (W5_REG_BASE + 0x130)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5 (W5_REG_BASE + 0x134)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6 (W5_REG_BASE + 0x138)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7 (W5_REG_BASE + 0x13C)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_8 (W5_REG_BASE + 0x140)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_9 (W5_REG_BASE + 0x144)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_10 (W5_REG_BASE + 0x148)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_11 (W5_REG_BASE + 0x14C)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_12 (W5_REG_BASE + 0x150)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_13 (W5_REG_BASE + 0x154)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_14 (W5_REG_BASE + 0x158)
|
||||
#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_15 (W5_REG_BASE + 0x15C)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - ENC_PIC */
|
||||
/************************************************************************/
|
||||
#define W5_CMD_ENC_BS_START_ADDR (W5_REG_BASE + 0x118)
|
||||
#define W5_CMD_ENC_BS_SIZE (W5_REG_BASE + 0x11C)
|
||||
#define W5_CMD_ENC_PIC_USE_SEC_AXI (W5_REG_BASE + 0x124)
|
||||
#define W5_CMD_ENC_PIC_REPORT_PARAM (W5_REG_BASE + 0x128)
|
||||
|
||||
#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM (W5_REG_BASE + 0x138)
|
||||
#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR (W5_REG_BASE + 0x13C)
|
||||
#define W5_CMD_ENC_PIC_SRC_PIC_IDX (W5_REG_BASE + 0x144)
|
||||
#define W5_CMD_ENC_PIC_SRC_ADDR_Y (W5_REG_BASE + 0x148)
|
||||
#define W5_CMD_ENC_PIC_SRC_ADDR_U (W5_REG_BASE + 0x14C)
|
||||
#define W5_CMD_ENC_PIC_SRC_ADDR_V (W5_REG_BASE + 0x150)
|
||||
#define W5_CMD_ENC_PIC_SRC_STRIDE (W5_REG_BASE + 0x154)
|
||||
#define W5_CMD_ENC_PIC_SRC_FORMAT (W5_REG_BASE + 0x158)
|
||||
#define W5_CMD_ENC_PIC_SRC_AXI_SEL (W5_REG_BASE + 0x160)
|
||||
#define W5_CMD_ENC_PIC_CODE_OPTION (W5_REG_BASE + 0x164)
|
||||
#define W5_CMD_ENC_PIC_PIC_PARAM (W5_REG_BASE + 0x168)
|
||||
#define W5_CMD_ENC_PIC_LONGTERM_PIC (W5_REG_BASE + 0x16C)
|
||||
#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y (W5_REG_BASE + 0x170)
|
||||
#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C (W5_REG_BASE + 0x174)
|
||||
#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y (W5_REG_BASE + 0x178)
|
||||
#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C (W5_REG_BASE + 0x17C)
|
||||
#define W5_CMD_ENC_PIC_CF50_Y_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x190)
|
||||
#define W5_CMD_ENC_PIC_CF50_CB_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x194)
|
||||
#define W5_CMD_ENC_PIC_CF50_CR_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x198)
|
||||
#define W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x180)
|
||||
#define W5_CMD_ENC_PIC_PREFIX_SEI_INFO (W5_REG_BASE + 0x184)
|
||||
#define W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x188)
|
||||
#define W5_CMD_ENC_PIC_SUFFIX_SEI_INFO (W5_REG_BASE + 0x18c)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - QUERY (GET_RESULT) */
|
||||
/************************************************************************/
|
||||
#define W5_RET_ENC_NUM_REQUIRED_FB (W5_REG_BASE + 0x11C)
|
||||
#define W5_RET_ENC_MIN_SRC_BUF_NUM (W5_REG_BASE + 0x120)
|
||||
#define W5_RET_ENC_PIC_TYPE (W5_REG_BASE + 0x124)
|
||||
/*
|
||||
* #define W5_RET_ENC_PIC_POC (W5_REG_BASE + 0x128)
|
||||
* => picture order count value of current encoded picture
|
||||
*/
|
||||
#define W5_RET_ENC_PIC_IDX (W5_REG_BASE + 0x12C)
|
||||
/*
|
||||
* #define W5_RET_ENC_PIC_SLICE_NUM (W5_REG_BASE + 0x130)
|
||||
* reg_val & 0xffff = total independent slice segment number (16 bits)
|
||||
* (reg_val >> 16) & 0xffff = total dependent slice segment number (16 bits)
|
||||
*
|
||||
* #define W5_RET_ENC_PIC_SKIP (W5_REG_BASE + 0x134)
|
||||
* reg_val & 0xfe = picture skip flag (7 bits)
|
||||
*
|
||||
* #define W5_RET_ENC_PIC_NUM_INTRA (W5_REG_BASE + 0x138)
|
||||
* => number of intra blocks in 8x8 (32 bits)
|
||||
*
|
||||
* #define W5_RET_ENC_PIC_NUM_MERGE (W5_REG_BASE + 0x13C)
|
||||
* => number of merge blocks in 8x8 (32 bits)
|
||||
*
|
||||
* #define W5_RET_ENC_PIC_NUM_SKIP (W5_REG_BASE + 0x144)
|
||||
* => number of skip blocks in 8x8 (32 bits)
|
||||
*
|
||||
* #define W5_RET_ENC_PIC_AVG_CTU_QP (W5_REG_BASE + 0x148)
|
||||
* => Average CTU QP value (32 bits)
|
||||
*/
|
||||
#define W5_RET_ENC_PIC_BYTE (W5_REG_BASE + 0x14C)
|
||||
/*
|
||||
* #define W5_RET_ENC_GOP_PIC_IDX (W5_REG_BASE + 0x150)
|
||||
* => picture index in group of pictures
|
||||
*/
|
||||
#define W5_RET_ENC_USED_SRC_IDX (W5_REG_BASE + 0x154)
|
||||
/*
|
||||
* #define W5_RET_ENC_PIC_NUM (W5_REG_BASE + 0x158)
|
||||
* => encoded picture number
|
||||
*/
|
||||
#define W5_RET_ENC_VCL_NUT (W5_REG_BASE + 0x15C)
|
||||
/*
|
||||
* Only for H264:
|
||||
* #define W5_RET_ENC_PIC_DIST_LOW (W5_REG_BASE + 0x164)
|
||||
* => lower 32 bits of the sum of squared difference between source Y picture
|
||||
* and reconstructed Y picture
|
||||
* #define W5_RET_ENC_PIC_DIST_HIGH (W5_REG_BASE + 0x168)
|
||||
* => upper 32 bits of the sum of squared difference between source Y picture
|
||||
* and reconstructed Y picture
|
||||
*/
|
||||
#define W5_RET_ENC_PIC_MAX_LATENCY_PICS (W5_REG_BASE + 0x16C)
|
||||
|
||||
#define W5_RET_ENC_HOST_CMD_TICK (W5_REG_BASE + 0x1B8)
|
||||
/*
|
||||
* #define W5_RET_ENC_PREPARE_START_TICK (W5_REG_BASE + 0x1BC)
|
||||
* #define W5_RET_ENC_PREPARE_END_TICK (W5_REG_BASE + 0x1C0)
|
||||
* => Start and end ticks for preparing slices of the picture
|
||||
* #define W5_RET_ENC_PROCESSING_START_TICK (W5_REG_BASE + 0x1C4)
|
||||
* #define W5_RET_ENC_PROCESSING_END_TICK (W5_REG_BASE + 0x1C8)
|
||||
* => Start and end ticks for processing slices of the picture
|
||||
* #define W5_RET_ENC_ENCODING_START_TICK (W5_REG_BASE + 0x1CC)
|
||||
* => Start tick for encoding slices of the picture
|
||||
*/
|
||||
#define W5_RET_ENC_ENCODING_END_TICK (W5_REG_BASE + 0x1D0)
|
||||
|
||||
#define W5_RET_ENC_WARN_INFO (W5_REG_BASE + 0x1D4)
|
||||
#define W5_RET_ENC_ERR_INFO (W5_REG_BASE + 0x1D8)
|
||||
#define W5_RET_ENC_ENCODING_SUCCESS (W5_REG_BASE + 0x1DC)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - QUERY (GET_BS_WR_PTR) */
|
||||
/************************************************************************/
|
||||
#define W5_RET_ENC_RD_PTR (W5_REG_BASE + 0x114)
|
||||
#define W5_RET_ENC_WR_PTR (W5_REG_BASE + 0x118)
|
||||
#define W5_CMD_ENC_REASON_SEL (W5_REG_BASE + 0x11C)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - QUERY (GET_BW_REPORT) */
|
||||
/************************************************************************/
|
||||
#define RET_QUERY_BW_PRP_AXI_READ (W5_REG_BASE + 0x118)
|
||||
#define RET_QUERY_BW_PRP_AXI_WRITE (W5_REG_BASE + 0x11C)
|
||||
#define RET_QUERY_BW_FBD_Y_AXI_READ (W5_REG_BASE + 0x120)
|
||||
#define RET_QUERY_BW_FBC_Y_AXI_WRITE (W5_REG_BASE + 0x124)
|
||||
#define RET_QUERY_BW_FBD_C_AXI_READ (W5_REG_BASE + 0x128)
|
||||
#define RET_QUERY_BW_FBC_C_AXI_WRITE (W5_REG_BASE + 0x12C)
|
||||
#define RET_QUERY_BW_PRI_AXI_READ (W5_REG_BASE + 0x130)
|
||||
#define RET_QUERY_BW_PRI_AXI_WRITE (W5_REG_BASE + 0x134)
|
||||
#define RET_QUERY_BW_SEC_AXI_READ (W5_REG_BASE + 0x138)
|
||||
#define RET_QUERY_BW_SEC_AXI_WRITE (W5_REG_BASE + 0x13C)
|
||||
#define RET_QUERY_BW_PROC_AXI_READ (W5_REG_BASE + 0x140)
|
||||
#define RET_QUERY_BW_PROC_AXI_WRITE (W5_REG_BASE + 0x144)
|
||||
#define RET_QUERY_BW_BWB_AXI_WRITE (W5_REG_BASE + 0x148)
|
||||
#define W5_CMD_BW_OPTION (W5_REG_BASE + 0x14C)
|
||||
|
||||
/************************************************************************/
|
||||
/* ENCODER - QUERY (GET_SRC_FLAG) */
|
||||
/************************************************************************/
|
||||
#define W5_RET_RELEASED_SRC_INSTANCE (W5_REG_BASE + 0x1EC)
|
||||
|
||||
#define W5_ENC_PIC_SUB_FRAME_SYNC_IF (W5_REG_BASE + 0x0300)
|
||||
|
||||
#endif /* __WAVE5_REGISTER_DEFINE_H__ */
|
||||
245
drivers/media/platform/chips-media/wave5/wave5-vdi.c
Normal file
245
drivers/media/platform/chips-media/wave5/wave5-vdi.c
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - low level access functions
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include "wave5-vdi.h"
|
||||
#include "wave5-vpu.h"
|
||||
#include "wave5-regdefine.h"
|
||||
#include <linux/delay.h>
|
||||
|
||||
#define VDI_SRAM_BASE_ADDR 0x00
|
||||
|
||||
#define VDI_SYSTEM_ENDIAN VDI_LITTLE_ENDIAN
|
||||
#define VDI_128BIT_BUS_SYSTEM_ENDIAN VDI_128BIT_LITTLE_ENDIAN
|
||||
|
||||
static int wave5_vdi_allocate_common_memory(struct device *dev)
|
||||
{
|
||||
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
|
||||
|
||||
if (!vpu_dev->common_mem.vaddr) {
|
||||
int ret;
|
||||
|
||||
vpu_dev->common_mem.size = SIZE_COMMON;
|
||||
ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vpu_dev->common_mem);
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to allocate common buffer\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(dev, "[VDI] common_mem: daddr=%pad size=%zu vaddr=0x%p\n",
|
||||
&vpu_dev->common_mem.daddr, vpu_dev->common_mem.size, vpu_dev->common_mem.vaddr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wave5_vdi_init(struct device *dev)
|
||||
{
|
||||
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = wave5_vdi_allocate_common_memory(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "[VDI] failed to get vpu common buffer from driver\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) {
|
||||
WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev->product_code);
|
||||
return 0;
|
||||
}
|
||||
|
||||
// if BIT processor is not running.
|
||||
if (wave5_vdi_readl(vpu_dev, W5_VCPU_CUR_PC) == 0) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 64; i++)
|
||||
wave5_vdi_write_register(vpu_dev, (i * 4) + 0x100, 0x0);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "[VDI] driver initialized successfully\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wave5_vdi_release(struct device *dev)
|
||||
{
|
||||
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
|
||||
|
||||
vpu_dev->vdb_register = NULL;
|
||||
wave5_vdi_free_dma_memory(vpu_dev, &vpu_dev->common_mem);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data)
|
||||
{
|
||||
writel(data, vpu_dev->vdb_register + addr);
|
||||
}
|
||||
|
||||
unsigned int wave5_vdi_readl(struct vpu_device *vpu_dev, u32 addr)
|
||||
{
|
||||
return readl(vpu_dev->vdb_register + addr);
|
||||
}
|
||||
|
||||
int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
|
||||
{
|
||||
if (!vb || !vb->vaddr) {
|
||||
dev_err(vpu_dev->dev, "%s: unable to clear unmapped buffer\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memset(vb->vaddr, 0, vb->size);
|
||||
return vb->size;
|
||||
}
|
||||
|
||||
static void wave5_swap_endian(struct vpu_device *vpu_dev, u8 *data, size_t len,
|
||||
unsigned int endian);
|
||||
|
||||
int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,
|
||||
u8 *data, size_t len, unsigned int endian)
|
||||
{
|
||||
if (!vb || !vb->vaddr) {
|
||||
dev_err(vpu_dev->dev, "%s: unable to write to unmapped buffer\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (offset > vb->size || len > vb->size || offset + len > vb->size) {
|
||||
dev_err(vpu_dev->dev, "%s: buffer too small\n", __func__);
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
wave5_swap_endian(vpu_dev, data, len, endian);
|
||||
memcpy(vb->vaddr + offset, data, len);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
|
||||
{
|
||||
void *vaddr;
|
||||
dma_addr_t daddr;
|
||||
|
||||
if (!vb->size) {
|
||||
dev_err(vpu_dev->dev, "%s: requested size==0\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
vaddr = dma_alloc_coherent(vpu_dev->dev, vb->size, &daddr, GFP_KERNEL);
|
||||
if (!vaddr)
|
||||
return -ENOMEM;
|
||||
vb->vaddr = vaddr;
|
||||
vb->daddr = daddr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
|
||||
{
|
||||
if (vb->size == 0)
|
||||
return;
|
||||
|
||||
if (!vb->vaddr)
|
||||
dev_err(vpu_dev->dev, "%s: requested free of unmapped buffer\n", __func__);
|
||||
else
|
||||
dma_free_coherent(vpu_dev->dev, vb->size, vb->vaddr, vb->daddr);
|
||||
|
||||
memset(vb, 0, sizeof(*vb));
|
||||
}
|
||||
|
||||
unsigned int wave5_vdi_convert_endian(struct vpu_device *vpu_dev, unsigned int endian)
|
||||
{
|
||||
if (PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) {
|
||||
switch (endian) {
|
||||
case VDI_LITTLE_ENDIAN:
|
||||
endian = 0x00;
|
||||
break;
|
||||
case VDI_BIG_ENDIAN:
|
||||
endian = 0x0f;
|
||||
break;
|
||||
case VDI_32BIT_LITTLE_ENDIAN:
|
||||
endian = 0x04;
|
||||
break;
|
||||
case VDI_32BIT_BIG_ENDIAN:
|
||||
endian = 0x03;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (endian & 0x0f);
|
||||
}
|
||||
|
||||
static void byte_swap(unsigned char *data, size_t len)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < len; i += 2)
|
||||
swap(data[i], data[i + 1]);
|
||||
}
|
||||
|
||||
static void word_swap(unsigned char *data, size_t len)
|
||||
{
|
||||
u16 *ptr = (u16 *)data;
|
||||
unsigned int i;
|
||||
size_t size = len / sizeof(uint16_t);
|
||||
|
||||
for (i = 0; i < size; i += 2)
|
||||
swap(ptr[i], ptr[i + 1]);
|
||||
}
|
||||
|
||||
static void dword_swap(unsigned char *data, size_t len)
|
||||
{
|
||||
u32 *ptr = (u32 *)data;
|
||||
size_t size = len / sizeof(u32);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < size; i += 2)
|
||||
swap(ptr[i], ptr[i + 1]);
|
||||
}
|
||||
|
||||
static void lword_swap(unsigned char *data, size_t len)
|
||||
{
|
||||
u64 *ptr = (u64 *)data;
|
||||
size_t size = len / sizeof(uint64_t);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < size; i += 2)
|
||||
swap(ptr[i], ptr[i + 1]);
|
||||
}
|
||||
|
||||
static void wave5_swap_endian(struct vpu_device *vpu_dev, u8 *data, size_t len,
|
||||
unsigned int endian)
|
||||
{
|
||||
int changes;
|
||||
unsigned int sys_endian = VDI_128BIT_BUS_SYSTEM_ENDIAN;
|
||||
bool byte_change, word_change, dword_change, lword_change;
|
||||
|
||||
if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) {
|
||||
dev_err(vpu_dev->dev, "unknown product id: %08x\n", vpu_dev->product_code);
|
||||
return;
|
||||
}
|
||||
|
||||
endian = wave5_vdi_convert_endian(vpu_dev, endian);
|
||||
sys_endian = wave5_vdi_convert_endian(vpu_dev, sys_endian);
|
||||
if (endian == sys_endian)
|
||||
return;
|
||||
|
||||
changes = endian ^ sys_endian;
|
||||
byte_change = changes & 0x01;
|
||||
word_change = ((changes & 0x02) == 0x02);
|
||||
dword_change = ((changes & 0x04) == 0x04);
|
||||
lword_change = ((changes & 0x08) == 0x08);
|
||||
|
||||
if (byte_change)
|
||||
byte_swap(data, len);
|
||||
if (word_change)
|
||||
word_swap(data, len);
|
||||
if (dword_change)
|
||||
dword_swap(data, len);
|
||||
if (lword_change)
|
||||
lword_swap(data, len);
|
||||
}
|
||||
67
drivers/media/platform/chips-media/wave5/wave5-vdi.h
Normal file
67
drivers/media/platform/chips-media/wave5/wave5-vdi.h
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - low level access functions
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
|
||||
#ifndef _VDI_H_
|
||||
#define _VDI_H_
|
||||
|
||||
#include "wave5-vpuconfig.h"
|
||||
#include <linux/string.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
/************************************************************************/
|
||||
/* COMMON REGISTERS */
|
||||
/************************************************************************/
|
||||
#define VPU_PRODUCT_CODE_REGISTER 0x1044
|
||||
|
||||
/* system register write */
|
||||
#define vpu_write_reg(VPU_INST, ADDR, DATA) wave5_vdi_write_register(VPU_INST, ADDR, DATA)
|
||||
/* system register read */
|
||||
#define vpu_read_reg(CORE, ADDR) wave5_vdi_readl(CORE, ADDR)
|
||||
|
||||
struct vpu_buf {
|
||||
size_t size;
|
||||
dma_addr_t daddr;
|
||||
void *vaddr;
|
||||
};
|
||||
|
||||
struct dma_vpu_buf {
|
||||
size_t size;
|
||||
dma_addr_t daddr;
|
||||
};
|
||||
|
||||
enum endian_mode {
|
||||
VDI_LITTLE_ENDIAN = 0, /* 64bit LE */
|
||||
VDI_BIG_ENDIAN, /* 64bit BE */
|
||||
VDI_32BIT_LITTLE_ENDIAN,
|
||||
VDI_32BIT_BIG_ENDIAN,
|
||||
/* WAVE PRODUCTS */
|
||||
VDI_128BIT_LITTLE_ENDIAN = 16,
|
||||
VDI_128BIT_LE_BYTE_SWAP,
|
||||
VDI_128BIT_LE_WORD_SWAP,
|
||||
VDI_128BIT_LE_WORD_BYTE_SWAP,
|
||||
VDI_128BIT_LE_DWORD_SWAP,
|
||||
VDI_128BIT_LE_DWORD_BYTE_SWAP,
|
||||
VDI_128BIT_LE_DWORD_WORD_SWAP,
|
||||
VDI_128BIT_LE_DWORD_WORD_BYTE_SWAP,
|
||||
VDI_128BIT_BE_DWORD_WORD_BYTE_SWAP,
|
||||
VDI_128BIT_BE_DWORD_WORD_SWAP,
|
||||
VDI_128BIT_BE_DWORD_BYTE_SWAP,
|
||||
VDI_128BIT_BE_DWORD_SWAP,
|
||||
VDI_128BIT_BE_WORD_BYTE_SWAP,
|
||||
VDI_128BIT_BE_WORD_SWAP,
|
||||
VDI_128BIT_BE_BYTE_SWAP,
|
||||
VDI_128BIT_BIG_ENDIAN = 31,
|
||||
VDI_ENDIAN_MAX
|
||||
};
|
||||
|
||||
#define VDI_128BIT_ENDIAN_MASK 0xf
|
||||
|
||||
int wave5_vdi_init(struct device *dev);
|
||||
int wave5_vdi_release(struct device *dev); //this function may be called only at system off.
|
||||
|
||||
#endif //#ifndef _VDI_H_
|
||||
1429
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
Normal file
1429
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
Normal file
File diff suppressed because it is too large
Load diff
1746
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
Normal file
1746
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
Normal file
File diff suppressed because it is too large
Load diff
362
drivers/media/platform/chips-media/wave5/wave5-vpu.c
Normal file
362
drivers/media/platform/chips-media/wave5/wave5-vpu.c
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - platform driver
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include "wave5-vpu.h"
|
||||
#include "wave5-regdefine.h"
|
||||
#include "wave5-vpuconfig.h"
|
||||
#include "wave5.h"
|
||||
|
||||
#define VPU_PLATFORM_DEVICE_NAME "vdec"
|
||||
#define VPU_CLK_NAME "vcodec"
|
||||
|
||||
#define WAVE5_IS_ENC BIT(0)
|
||||
#define WAVE5_IS_DEC BIT(1)
|
||||
|
||||
struct wave5_match_data {
|
||||
int flags;
|
||||
const char *fw_name;
|
||||
};
|
||||
|
||||
int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = wait_for_completion_timeout(&inst->irq_done,
|
||||
msecs_to_jiffies(timeout));
|
||||
if (!ret)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
reinit_completion(&inst->irq_done);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void wave5_vpu_get_interrupt_for_inst(struct vpu_instance *inst, u32 status)
|
||||
{
|
||||
struct vpu_device *dev = inst->dev;
|
||||
u32 seq_done;
|
||||
u32 cmd_done;
|
||||
int val;
|
||||
|
||||
seq_done = wave5_vdi_readl(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);
|
||||
cmd_done = wave5_vdi_readl(dev, W5_RET_QUEUE_CMD_DONE_INST);
|
||||
|
||||
if (status & BIT(INT_WAVE5_INIT_SEQ)) {
|
||||
if (seq_done & BIT(inst->id)) {
|
||||
seq_done &= ~BIT(inst->id);
|
||||
wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done);
|
||||
val = BIT(INT_WAVE5_INIT_SEQ);
|
||||
kfifo_in(&inst->irq_status, &val, sizeof(int));
|
||||
}
|
||||
}
|
||||
if (status & BIT(INT_WAVE5_ENC_SET_PARAM)) {
|
||||
if (seq_done & BIT(inst->id)) {
|
||||
seq_done &= ~BIT(inst->id);
|
||||
wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done);
|
||||
val = BIT(INT_WAVE5_ENC_SET_PARAM);
|
||||
kfifo_in(&inst->irq_status, &val, sizeof(int));
|
||||
}
|
||||
}
|
||||
if (status & BIT(INT_WAVE5_DEC_PIC) ||
|
||||
status & BIT(INT_WAVE5_ENC_PIC)) {
|
||||
if (cmd_done & BIT(inst->id)) {
|
||||
cmd_done &= ~BIT(inst->id);
|
||||
wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, cmd_done);
|
||||
val = BIT(INT_WAVE5_DEC_PIC);
|
||||
kfifo_in(&inst->irq_status, &val, sizeof(int));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t wave5_vpu_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct vpu_device *dev = dev_id;
|
||||
|
||||
if (wave5_vdi_readl(dev, W5_VPU_VPU_INT_STS)) {
|
||||
struct vpu_instance *inst;
|
||||
u32 irq_status = wave5_vdi_readl(dev, W5_VPU_VINT_REASON);
|
||||
|
||||
list_for_each_entry(inst, &dev->instances, list) {
|
||||
wave5_vpu_get_interrupt_for_inst(inst, irq_status);
|
||||
}
|
||||
|
||||
wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_status);
|
||||
wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1);
|
||||
|
||||
return IRQ_WAKE_THREAD;
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id)
|
||||
{
|
||||
struct vpu_device *dev = dev_id;
|
||||
struct vpu_instance *inst;
|
||||
int irq_status, ret;
|
||||
u32 val;
|
||||
|
||||
list_for_each_entry(inst, &dev->instances, list) {
|
||||
while (kfifo_len(&inst->irq_status)) {
|
||||
struct vpu_instance *curr;
|
||||
|
||||
curr = v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev);
|
||||
if (curr) {
|
||||
inst->ops->finish_process(inst);
|
||||
} else {
|
||||
ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
|
||||
if (!ret)
|
||||
break;
|
||||
|
||||
val = wave5_vdi_readl(dev, W5_VPU_VINT_REASON_USR);
|
||||
val &= ~irq_status;
|
||||
wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_USR, val);
|
||||
complete(&inst->irq_done);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name)
|
||||
{
|
||||
const struct firmware *fw;
|
||||
int ret;
|
||||
u32 revision;
|
||||
unsigned int product_id;
|
||||
|
||||
ret = request_firmware(&fw, fw_name, dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "request_firmware, fail: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size);
|
||||
if (ret) {
|
||||
dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret);
|
||||
goto release_fw;
|
||||
}
|
||||
release_firmware(fw);
|
||||
|
||||
ret = wave5_vpu_get_version_info(dev, &revision, &product_id);
|
||||
if (ret) {
|
||||
dev_err(dev, "vpu_get_version_info fail: %d\n", ret);
|
||||
goto err_without_release;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n",
|
||||
__func__, product_id, revision);
|
||||
|
||||
return 0;
|
||||
|
||||
release_fw:
|
||||
release_firmware(fw);
|
||||
err_without_release:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wave5_vpu_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct vpu_device *dev;
|
||||
struct device_node *np;
|
||||
const struct wave5_match_data *match_data;
|
||||
struct resource sram;
|
||||
|
||||
match_data = device_get_match_data(&pdev->dev);
|
||||
if (!match_data) {
|
||||
dev_err(&pdev->dev, "missing device match data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* physical addresses limited to 32 bits */
|
||||
dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
|
||||
dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
|
||||
|
||||
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
||||
if (!dev)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->vdb_register = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(dev->vdb_register))
|
||||
return PTR_ERR(dev->vdb_register);
|
||||
ida_init(&dev->inst_ida);
|
||||
|
||||
mutex_init(&dev->dev_lock);
|
||||
mutex_init(&dev->hw_lock);
|
||||
dev_set_drvdata(&pdev->dev, dev);
|
||||
dev->dev = &pdev->dev;
|
||||
|
||||
ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks);
|
||||
|
||||
/* continue without clock, assume externally managed */
|
||||
if (ret < 0) {
|
||||
dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret);
|
||||
ret = 0;
|
||||
}
|
||||
dev->num_clks = ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
np = of_parse_phandle(pdev->dev.of_node, "sram", 0);
|
||||
if (!np) {
|
||||
dev_warn(&pdev->dev, "sram node not found\n");
|
||||
} else {
|
||||
ret = of_address_to_resource(np, 0, &sram);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "sram resource not available\n");
|
||||
goto err_put_node;
|
||||
}
|
||||
dev->sram_buf.daddr = sram.start;
|
||||
dev->sram_buf.size = resource_size(&sram);
|
||||
dev_dbg(&pdev->dev, "%s: sram daddr: %pad, size: 0x%lx\n",
|
||||
__func__, &dev->sram_buf.daddr, dev->sram_buf.size);
|
||||
}
|
||||
|
||||
dev->product_code = wave5_vdi_readl(dev, VPU_PRODUCT_CODE_REGISTER);
|
||||
ret = wave5_vdi_init(&pdev->dev);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret);
|
||||
goto err_clk_dis;
|
||||
}
|
||||
dev->product = wave5_vpu_get_product_id(dev);
|
||||
|
||||
INIT_LIST_HEAD(&dev->instances);
|
||||
ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret);
|
||||
goto err_vdi_release;
|
||||
}
|
||||
|
||||
if (match_data->flags & WAVE5_IS_DEC) {
|
||||
ret = wave5_vpu_dec_register_device(dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret);
|
||||
goto err_v4l2_unregister;
|
||||
}
|
||||
}
|
||||
if (match_data->flags & WAVE5_IS_ENC) {
|
||||
ret = wave5_vpu_enc_register_device(dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret);
|
||||
goto err_dec_unreg;
|
||||
}
|
||||
}
|
||||
|
||||
dev->irq = platform_get_irq(pdev, 0);
|
||||
if (dev->irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get irq resource\n");
|
||||
ret = -ENXIO;
|
||||
goto err_enc_unreg;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq,
|
||||
wave5_vpu_irq_thread, 0, "vpu_irq", dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret);
|
||||
goto err_enc_unreg;
|
||||
}
|
||||
|
||||
ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret);
|
||||
goto err_enc_unreg;
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s and product code: 0x%x\n",
|
||||
(match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "",
|
||||
(match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "",
|
||||
dev->product_code);
|
||||
return 0;
|
||||
|
||||
err_enc_unreg:
|
||||
if (match_data->flags & WAVE5_IS_ENC)
|
||||
wave5_vpu_enc_unregister_device(dev);
|
||||
err_dec_unreg:
|
||||
if (match_data->flags & WAVE5_IS_DEC)
|
||||
wave5_vpu_dec_unregister_device(dev);
|
||||
err_v4l2_unregister:
|
||||
v4l2_device_unregister(&dev->v4l2_dev);
|
||||
err_vdi_release:
|
||||
wave5_vdi_release(&pdev->dev);
|
||||
err_clk_dis:
|
||||
clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
|
||||
err_put_node:
|
||||
of_node_put(np);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wave5_vpu_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct vpu_device *dev = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
|
||||
wave5_vpu_enc_unregister_device(dev);
|
||||
wave5_vpu_dec_unregister_device(dev);
|
||||
v4l2_device_unregister(&dev->v4l2_dev);
|
||||
wave5_vdi_release(&pdev->dev);
|
||||
ida_destroy(&dev->inst_ida);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct wave5_match_data wave511_data = {
|
||||
.flags = WAVE5_IS_DEC,
|
||||
.fw_name = "wave511_dec_fw.bin",
|
||||
};
|
||||
|
||||
static const struct wave5_match_data wave521_data = {
|
||||
.flags = WAVE5_IS_ENC,
|
||||
.fw_name = "wave521_enc_fw.bin",
|
||||
};
|
||||
|
||||
static const struct wave5_match_data wave521c_data = {
|
||||
.flags = WAVE5_IS_ENC | WAVE5_IS_DEC,
|
||||
.fw_name = "wave521c_codec_fw.bin",
|
||||
};
|
||||
|
||||
static const struct wave5_match_data default_match_data = {
|
||||
.flags = WAVE5_IS_ENC | WAVE5_IS_DEC,
|
||||
.fw_name = "chagall.bin",
|
||||
};
|
||||
|
||||
static const struct of_device_id wave5_dt_ids[] = {
|
||||
{ .compatible = "cnm,cm511-vpu", .data = &wave511_data },
|
||||
{ .compatible = "cnm,cm517-vpu", .data = &default_match_data },
|
||||
{ .compatible = "cnm,cm521-vpu", .data = &wave521_data },
|
||||
{ .compatible = "cnm,cm521c-vpu", .data = &wave521c_data },
|
||||
{ .compatible = "cnm,cm521c-dual-vpu", .data = &wave521c_data },
|
||||
{ .compatible = "cnm,cm521e1-vpu", .data = &default_match_data },
|
||||
{ .compatible = "cnm,cm537-vpu", .data = &default_match_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, wave5_dt_ids);
|
||||
|
||||
static struct platform_driver wave5_vpu_driver = {
|
||||
.driver = {
|
||||
.name = VPU_PLATFORM_DEVICE_NAME,
|
||||
.of_match_table = of_match_ptr(wave5_dt_ids),
|
||||
},
|
||||
.probe = wave5_vpu_probe,
|
||||
.remove = wave5_vpu_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(wave5_vpu_driver);
|
||||
MODULE_DESCRIPTION("chips&media VPU V4L2 driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
72
drivers/media/platform/chips-media/wave5/wave5-vpu.h
Normal file
72
drivers/media/platform/chips-media/wave5/wave5-vpu.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - basic types
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
#ifndef __VPU_DRV_H__
|
||||
#define __VPU_DRV_H__
|
||||
|
||||
#include <media/v4l2-ctrls.h>
|
||||
#include <media/v4l2-ioctl.h>
|
||||
#include <media/v4l2-event.h>
|
||||
#include <media/v4l2-fh.h>
|
||||
#include <media/videobuf2-v4l2.h>
|
||||
#include <media/videobuf2-dma-contig.h>
|
||||
#include <media/videobuf2-vmalloc.h>
|
||||
#include "wave5-vpuconfig.h"
|
||||
#include "wave5-vpuapi.h"
|
||||
|
||||
#define VPU_BUF_SYNC_TO_DEVICE 0
|
||||
#define VPU_BUF_SYNC_FROM_DEVICE 1
|
||||
|
||||
struct vpu_buffer {
|
||||
struct v4l2_m2m_buffer v4l2_m2m_buf;
|
||||
bool consumed;
|
||||
};
|
||||
|
||||
enum vpu_fmt_type {
|
||||
VPU_FMT_TYPE_CODEC = 0,
|
||||
VPU_FMT_TYPE_RAW = 1
|
||||
};
|
||||
|
||||
struct vpu_format {
|
||||
unsigned int v4l2_pix_fmt;
|
||||
unsigned int max_width;
|
||||
unsigned int min_width;
|
||||
unsigned int max_height;
|
||||
unsigned int min_height;
|
||||
};
|
||||
|
||||
static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh)
|
||||
{
|
||||
return container_of(vfh, struct vpu_instance, v4l2_fh);
|
||||
}
|
||||
|
||||
static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl)
|
||||
{
|
||||
return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl);
|
||||
}
|
||||
|
||||
static inline struct vpu_buffer *wave5_to_vpu_buf(struct vb2_v4l2_buffer *vbuf)
|
||||
{
|
||||
return container_of(vbuf, struct vpu_buffer, v4l2_m2m_buf.vb);
|
||||
}
|
||||
|
||||
int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout);
|
||||
|
||||
int wave5_vpu_dec_register_device(struct vpu_device *dev);
|
||||
void wave5_vpu_dec_unregister_device(struct vpu_device *dev);
|
||||
int wave5_vpu_enc_register_device(struct vpu_device *dev);
|
||||
void wave5_vpu_enc_unregister_device(struct vpu_device *dev);
|
||||
static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst)
|
||||
{
|
||||
struct vb2_queue *vq_cap =
|
||||
v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
|
||||
struct vb2_queue *vq_out =
|
||||
v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
|
||||
|
||||
return vb2_is_streaming(vq_cap) && vb2_is_streaming(vq_out);
|
||||
}
|
||||
|
||||
#endif
|
||||
1040
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
Normal file
1040
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
Normal file
File diff suppressed because it is too large
Load diff
1136
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
Normal file
1136
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
Normal file
File diff suppressed because it is too large
Load diff
90
drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h
Normal file
90
drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - product config definitions
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
|
||||
#ifndef _VPU_CONFIG_H_
|
||||
#define _VPU_CONFIG_H_
|
||||
|
||||
#define WAVE517_CODE 0x5170
|
||||
#define WAVE537_CODE 0x5370
|
||||
#define WAVE511_CODE 0x5110
|
||||
#define WAVE521_CODE 0x5210
|
||||
#define WAVE521C_CODE 0x521c
|
||||
#define WAVE521C_DUAL_CODE 0x521d // wave521 dual core
|
||||
#define WAVE521E1_CODE 0x5211
|
||||
|
||||
#define PRODUCT_CODE_W_SERIES(x) ({ \
|
||||
int c = x; \
|
||||
((c) == WAVE517_CODE || (c) == WAVE537_CODE || \
|
||||
(c) == WAVE511_CODE || (c) == WAVE521_CODE || \
|
||||
(c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \
|
||||
(c) == WAVE521C_DUAL_CODE); \
|
||||
})
|
||||
|
||||
#define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024)
|
||||
#define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K
|
||||
#define WAVE521DEC_WORKBUF_SIZE (1784 * 1024)
|
||||
|
||||
#define MAX_NUM_INSTANCE 32
|
||||
|
||||
#define W5_MIN_ENC_PIC_WIDTH 256
|
||||
#define W5_MIN_ENC_PIC_HEIGHT 128
|
||||
#define W5_MAX_ENC_PIC_WIDTH 8192
|
||||
#define W5_MAX_ENC_PIC_HEIGHT 8192
|
||||
|
||||
// application specific configuration
|
||||
#define VPU_ENC_TIMEOUT 60000
|
||||
#define VPU_DEC_TIMEOUT 60000
|
||||
|
||||
#define HOST_ENDIAN VDI_128BIT_LITTLE_ENDIAN
|
||||
#define VPU_FRAME_ENDIAN HOST_ENDIAN
|
||||
#define VPU_STREAM_ENDIAN HOST_ENDIAN
|
||||
#define VPU_USER_DATA_ENDIAN HOST_ENDIAN
|
||||
#define VPU_SOURCE_ENDIAN HOST_ENDIAN
|
||||
|
||||
// for WAVE encoder
|
||||
#define USE_SRC_PRP_AXI 0
|
||||
#define USE_SRC_PRI_AXI 1
|
||||
#define DEFAULT_SRC_AXI USE_SRC_PRP_AXI
|
||||
|
||||
/************************************************************************/
|
||||
/* VPU COMMON MEMORY */
|
||||
/************************************************************************/
|
||||
#define VLC_BUF_NUM (3)
|
||||
|
||||
#define COMMAND_QUEUE_DEPTH (4)
|
||||
|
||||
#define W5_REMAP_INDEX0 0
|
||||
#define W5_REMAP_INDEX1 1
|
||||
#define W5_REMAP_MAX_SIZE (1024 * 1024)
|
||||
|
||||
#define WAVE5_MAX_CODE_BUF_SIZE (2 * 1024 * 1024)
|
||||
#define WAVE5_TEMPBUF_OFFSET WAVE5_MAX_CODE_BUF_SIZE
|
||||
#define WAVE5_TEMPBUF_SIZE (1024 * 1024)
|
||||
|
||||
#define SIZE_COMMON (WAVE5_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE)
|
||||
|
||||
//=====4. VPU REPORT MEMORY ======================//
|
||||
|
||||
#define WAVE5_UPPER_PROC_AXI_ID 0x0
|
||||
|
||||
#define WAVE5_PROC_AXI_ID 0x0
|
||||
#define WAVE5_PRP_AXI_ID 0x0
|
||||
#define WAVE5_FBD_Y_AXI_ID 0x0
|
||||
#define WAVE5_FBC_Y_AXI_ID 0x0
|
||||
#define WAVE5_FBD_C_AXI_ID 0x0
|
||||
#define WAVE5_FBC_C_AXI_ID 0x0
|
||||
#define WAVE5_SEC_AXI_ID 0x0
|
||||
#define WAVE5_PRI_AXI_ID 0x0
|
||||
|
||||
#define WAVE5_PROC_AXI_AXPROT 0x0
|
||||
#define WAVE5_PROC_AXI_AXCACHE 0x0
|
||||
#define WAVE5_PROC_AXI_EXT_ADDR 0x0
|
||||
#define WAVE5_SEC_AXI_AXPROT 0x0
|
||||
#define WAVE5_SEC_AXI_AXCACHE 0x0
|
||||
#define WAVE5_SEC_AXI_EXT_ADDR 0x0
|
||||
|
||||
#endif /* _VPU_CONFIG_H_ */
|
||||
454
drivers/media/platform/chips-media/wave5/wave5-vpuerror.h
Normal file
454
drivers/media/platform/chips-media/wave5/wave5-vpuerror.h
Normal file
|
|
@ -0,0 +1,454 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - error values
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
|
||||
#ifndef ERROR_CODE_H_INCLUDED
|
||||
#define ERROR_CODE_H_INCLUDED
|
||||
|
||||
/*
|
||||
* WAVE5
|
||||
*/
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 COMMON SYSTEM ERROR (FAIL_REASON) */
|
||||
/************************************************************************/
|
||||
#define WAVE5_SYSERR_QUEUEING_FAIL 0x00000001
|
||||
#define WAVE5_SYSERR_ACCESS_VIOLATION_HW 0x00000040
|
||||
#define WAVE5_SYSERR_BUS_ERROR 0x00000200
|
||||
#define WAVE5_SYSERR_DOUBLE_FAULT 0x00000400
|
||||
#define WAVE5_SYSERR_RESULT_NOT_READY 0x00000800
|
||||
#define WAVE5_SYSERR_VPU_STILL_RUNNING 0x00001000
|
||||
#define WAVE5_SYSERR_UNKNOWN_CMD 0x00002000
|
||||
#define WAVE5_SYSERR_UNKNOWN_CODEC_STD 0x00004000
|
||||
#define WAVE5_SYSERR_UNKNOWN_QUERY_OPTION 0x00008000
|
||||
#define WAVE5_SYSERR_VLC_BUF_FULL 0x00010000
|
||||
#define WAVE5_SYSERR_WATCHDOG_TIMEOUT 0x00020000
|
||||
#define WAVE5_SYSERR_VCPU_TIMEOUT 0x00080000
|
||||
#define WAVE5_SYSERR_TEMP_SEC_BUF_OVERFLOW 0x00200000
|
||||
#define WAVE5_SYSERR_NEED_MORE_TASK_BUF 0x00400000
|
||||
#define WAVE5_SYSERR_PRESCAN_ERR 0x00800000
|
||||
#define WAVE5_SYSERR_ENC_GBIN_OVERCONSUME 0x01000000
|
||||
#define WAVE5_SYSERR_ENC_MAX_ZERO_DETECT 0x02000000
|
||||
#define WAVE5_SYSERR_ENC_LVL_FIRST_ERROR 0x04000000
|
||||
#define WAVE5_SYSERR_ENC_EG_RANGE_OVER 0x08000000
|
||||
#define WAVE5_SYSERR_ENC_IRB_FRAME_DROP 0x10000000
|
||||
#define WAVE5_SYSERR_INPLACE_V 0x20000000
|
||||
#define WAVE5_SYSERR_FATAL_VPU_HANGUP 0xf0000000
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 COMMAND QUEUE ERROR (FAIL_REASON) */
|
||||
/************************************************************************/
|
||||
#define WAVE5_CMDQ_ERR_NOT_QUEABLE_CMD 0x00000001
|
||||
#define WAVE5_CMDQ_ERR_SKIP_MODE_ENABLE 0x00000002
|
||||
#define WAVE5_CMDQ_ERR_INST_FLUSHING 0x00000003
|
||||
#define WAVE5_CMDQ_ERR_INST_INACTIVE 0x00000004
|
||||
#define WAVE5_CMDQ_ERR_QUEUE_FAIL 0x00000005
|
||||
#define WAVE5_CMDQ_ERR_CMD_BUF_FULL 0x00000006
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 ERROR ON DECODER (ERR_INFO) */
|
||||
/************************************************************************/
|
||||
// HEVC
|
||||
#define HEVC_SPSERR_SEQ_PARAMETER_SET_ID 0x00001000
|
||||
#define HEVC_SPSERR_CHROMA_FORMAT_IDC 0x00001001
|
||||
#define HEVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES 0x00001002
|
||||
#define HEVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES 0x00001003
|
||||
#define HEVC_SPSERR_CONF_WIN_LEFT_OFFSET 0x00001004
|
||||
#define HEVC_SPSERR_CONF_WIN_RIGHT_OFFSET 0x00001005
|
||||
#define HEVC_SPSERR_CONF_WIN_TOP_OFFSET 0x00001006
|
||||
#define HEVC_SPSERR_CONF_WIN_BOTTOM_OFFSET 0x00001007
|
||||
#define HEVC_SPSERR_BIT_DEPTH_LUMA_MINUS8 0x00001008
|
||||
#define HEVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8 0x00001009
|
||||
#define HEVC_SPSERR_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 0x0000100A
|
||||
#define HEVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING 0x0000100B
|
||||
#define HEVC_SPSERR_SPS_MAX_NUM_REORDER_PICS 0x0000100C
|
||||
#define HEVC_SPSERR_SPS_MAX_LATENCY_INCREASE 0x0000100D
|
||||
#define HEVC_SPSERR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3 0x0000100E
|
||||
#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE 0x0000100F
|
||||
#define HEVC_SPSERR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2 0x00001010
|
||||
#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE 0x00001011
|
||||
#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER 0x00001012
|
||||
#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA 0x00001013
|
||||
#define HEVC_SPSERR_SCALING_LIST 0x00001014
|
||||
#define HEVC_SPSERR_LOG2_DIFF_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3 0x00001015
|
||||
#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE 0x00001016
|
||||
#define HEVC_SPSERR_NUM_SHORT_TERM_REF_PIC_SETS 0x00001017
|
||||
#define HEVC_SPSERR_NUM_LONG_TERM_REF_PICS_SPS 0x00001018
|
||||
#define HEVC_SPSERR_GBU_PARSING_ERROR 0x00001019
|
||||
#define HEVC_SPSERR_EXTENSION_FLAG 0x0000101A
|
||||
#define HEVC_SPSERR_VUI_ERROR 0x0000101B
|
||||
#define HEVC_SPSERR_ACTIVATE_SPS 0x0000101C
|
||||
#define HEVC_SPSERR_PROFILE_SPACE 0x0000101D
|
||||
#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID 0x00002000
|
||||
#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID 0x00002001
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1 0x00002002
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1 0x00002003
|
||||
#define HEVC_PPSERR_INIT_QP_MINUS26 0x00002004
|
||||
#define HEVC_PPSERR_DIFF_CU_QP_DELTA_DEPTH 0x00002005
|
||||
#define HEVC_PPSERR_PPS_CB_QP_OFFSET 0x00002006
|
||||
#define HEVC_PPSERR_PPS_CR_QP_OFFSET 0x00002007
|
||||
#define HEVC_PPSERR_NUM_TILE_COLUMNS_MINUS1 0x00002008
|
||||
#define HEVC_PPSERR_NUM_TILE_ROWS_MINUS1 0x00002009
|
||||
#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1 0x0000200A
|
||||
#define HEVC_PPSERR_ROW_HEIGHT_MINUS1 0x0000200B
|
||||
#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2 0x0000200C
|
||||
#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2 0x0000200D
|
||||
#define HEVC_PPSERR_SCALING_LIST 0x0000200E
|
||||
#define HEVC_PPSERR_LOG2_PARALLEL_MERGE_LEVEL_MINUS2 0x0000200F
|
||||
#define HEVC_PPSERR_NUM_TILE_COLUMNS_RANGE_OUT 0x00002010
|
||||
#define HEVC_PPSERR_NUM_TILE_ROWS_RANGE_OUT 0x00002011
|
||||
#define HEVC_PPSERR_MORE_RBSP_DATA_ERROR 0x00002012
|
||||
#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT 0x00002013
|
||||
#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT 0x00002014
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002015
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002016
|
||||
#define HEVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT 0x00002017
|
||||
#define HEVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT 0x00002018
|
||||
#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1_RANGE_OUT 0x00002019
|
||||
#define HEVC_PPSERR_ROW_HEIGHT_MINUS1_RANGE_OUT 0x00002020
|
||||
#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2_RANGE_OUT 0x00002021
|
||||
#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2_RANGE_OUT 0x00002022
|
||||
#define HEVC_SHERR_SLICE_PIC_PARAMETER_SET_ID 0x00003000
|
||||
#define HEVC_SHERR_ACTIVATE_PPS 0x00003001
|
||||
#define HEVC_SHERR_ACTIVATE_SPS 0x00003002
|
||||
#define HEVC_SHERR_SLICE_TYPE 0x00003003
|
||||
#define HEVC_SHERR_FIRST_SLICE_IS_DEPENDENT_SLICE 0x00003004
|
||||
#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_SPS_FLAG 0x00003005
|
||||
#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET 0x00003006
|
||||
#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_IDX 0x00003007
|
||||
#define HEVC_SHERR_NUM_LONG_TERM_SPS 0x00003008
|
||||
#define HEVC_SHERR_NUM_LONG_TERM_PICS 0x00003009
|
||||
#define HEVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE 0x0000300A
|
||||
#define HEVC_SHERR_DELTA_POC_MSB_CYCLE_LT 0x0000300B
|
||||
#define HEVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1 0x0000300C
|
||||
#define HEVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1 0x0000300D
|
||||
#define HEVC_SHERR_COLLOCATED_REF_IDX 0x0000300E
|
||||
#define HEVC_SHERR_PRED_WEIGHT_TABLE 0x0000300F
|
||||
#define HEVC_SHERR_FIVE_MINUS_MAX_NUM_MERGE_CAND 0x00003010
|
||||
#define HEVC_SHERR_SLICE_QP_DELTA 0x00003011
|
||||
#define HEVC_SHERR_SLICE_QP_DELTA_IS_OUT_OF_RANGE 0x00003012
|
||||
#define HEVC_SHERR_SLICE_CB_QP_OFFSET 0x00003013
|
||||
#define HEVC_SHERR_SLICE_CR_QP_OFFSET 0x00003014
|
||||
#define HEVC_SHERR_SLICE_BETA_OFFSET_DIV2 0x00003015
|
||||
#define HEVC_SHERR_SLICE_TC_OFFSET_DIV2 0x00003016
|
||||
#define HEVC_SHERR_NUM_ENTRY_POINT_OFFSETS 0x00003017
|
||||
#define HEVC_SHERR_OFFSET_LEN_MINUS1 0x00003018
|
||||
#define HEVC_SHERR_SLICE_SEGMENT_HEADER_EXTENSION_LENGTH 0x00003019
|
||||
#define HEVC_SHERR_WRONG_POC_IN_STILL_PICTURE_PROFILE 0x0000301A
|
||||
#define HEVC_SHERR_SLICE_TYPE_ERROR_IN_STILL_PICTURE_PROFILE 0x0000301B
|
||||
#define HEVC_SHERR_PPS_ID_NOT_EQUAL_PREV_VALUE 0x0000301C
|
||||
#define HEVC_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000
|
||||
#define HEVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001
|
||||
#define HEVC_SPECERR_OVER_CHROMA_FORMAT 0x00004002
|
||||
#define HEVC_SPECERR_OVER_BIT_DEPTH 0x00004003
|
||||
#define HEVC_SPECERR_OVER_BUFFER_OVER_FLOW 0x00004004
|
||||
#define HEVC_SPECERR_OVER_WRONG_BUFFER_ACCESS 0x00004005
|
||||
#define HEVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND 0x00005000
|
||||
#define HEVC_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001
|
||||
#define HEVC_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002
|
||||
#define HEVC_ETCERR_INPLACE_V 0x0000500F
|
||||
|
||||
// AVC
|
||||
#define AVC_SPSERR_SEQ_PARAMETER_SET_ID 0x00001000
|
||||
#define AVC_SPSERR_CHROMA_FORMAT_IDC 0x00001001
|
||||
#define AVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES 0x00001002
|
||||
#define AVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES 0x00001003
|
||||
#define AVC_SPSERR_CONF_WIN_LEFT_OFFSET 0x00001004
|
||||
#define AVC_SPSERR_CONF_WIN_RIGHT_OFFSET 0x00001005
|
||||
#define AVC_SPSERR_CONF_WIN_TOP_OFFSET 0x00001006
|
||||
#define AVC_SPSERR_CONF_WIN_BOTTOM_OFFSET 0x00001007
|
||||
#define AVC_SPSERR_BIT_DEPTH_LUMA_MINUS8 0x00001008
|
||||
#define AVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8 0x00001009
|
||||
#define AVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING 0x0000100B
|
||||
#define AVC_SPSERR_SPS_MAX_NUM_REORDER_PICS 0x0000100C
|
||||
#define AVC_SPSERR_SCALING_LIST 0x00001014
|
||||
#define AVC_SPSERR_GBU_PARSING_ERROR 0x00001019
|
||||
#define AVC_SPSERR_VUI_ERROR 0x0000101B
|
||||
#define AVC_SPSERR_ACTIVATE_SPS 0x0000101C
|
||||
#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID 0x00002000
|
||||
#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID 0x00002001
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1 0x00002002
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1 0x00002003
|
||||
#define AVC_PPSERR_INIT_QP_MINUS26 0x00002004
|
||||
#define AVC_PPSERR_PPS_CB_QP_OFFSET 0x00002006
|
||||
#define AVC_PPSERR_PPS_CR_QP_OFFSET 0x00002007
|
||||
#define AVC_PPSERR_SCALING_LIST 0x0000200E
|
||||
#define AVC_PPSERR_MORE_RBSP_DATA_ERROR 0x00002012
|
||||
#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT 0x00002013
|
||||
#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT 0x00002014
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002015
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002016
|
||||
#define AVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT 0x00002017
|
||||
#define AVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT 0x00002018
|
||||
#define AVC_SHERR_SLICE_PIC_PARAMETER_SET_ID 0x00003000
|
||||
#define AVC_SHERR_ACTIVATE_PPS 0x00003001
|
||||
#define AVC_SHERR_ACTIVATE_SPS 0x00003002
|
||||
#define AVC_SHERR_SLICE_TYPE 0x00003003
|
||||
#define AVC_SHERR_FIRST_MB_IN_SLICE 0x00003004
|
||||
#define AVC_SHERR_RPLM 0x00003006
|
||||
#define AVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE 0x0000300A
|
||||
#define AVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1 0x0000300C
|
||||
#define AVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1 0x0000300D
|
||||
#define AVC_SHERR_PRED_WEIGHT_TABLE 0x0000300F
|
||||
#define AVC_SHERR_SLICE_QP_DELTA 0x00003011
|
||||
#define AVC_SHERR_SLICE_BETA_OFFSET_DIV2 0x00003015
|
||||
#define AVC_SHERR_SLICE_TC_OFFSET_DIV2 0x00003016
|
||||
#define AVC_SHERR_DISABLE_DEBLOCK_FILTER_IDC 0x00003017
|
||||
#define AVC_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000
|
||||
#define AVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001
|
||||
#define AVC_SPECERR_OVER_CHROMA_FORMAT 0x00004002
|
||||
#define AVC_SPECERR_OVER_BIT_DEPTH 0x00004003
|
||||
#define AVC_SPECERR_OVER_BUFFER_OVER_FLOW 0x00004004
|
||||
#define AVC_SPECERR_OVER_WRONG_BUFFER_ACCESS 0x00004005
|
||||
#define AVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND 0x00005000
|
||||
#define AVC_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001
|
||||
#define AVC_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002
|
||||
#define AVC_ETCERR_ASO 0x00005004
|
||||
#define AVC_ETCERR_FMO 0x00005005
|
||||
#define AVC_ETCERR_INPLACE_V 0x0000500F
|
||||
|
||||
// AV1
|
||||
#define AV1_SPSERR_MAX_FRAME_WIDTH 0x00001001
|
||||
#define AV1_SPSERR_MAX_FRAME_HEIGHT 0x00001002
|
||||
#define AV1_SPSERR_ID_LEN_EXCEED_16 0x00001004
|
||||
#define AV1_SPSERR_NOT_FOUND_FIRST_SPS 0x0000100A
|
||||
#define AV1_SPSERR_SEQ_PROFILE 0x0000100B
|
||||
#define AV1_SPSERR_STILL_PICTURE 0x0000100C
|
||||
#define AV1_PPSERR_FRAME_SIZE_WIDTH 0x00002001
|
||||
#define AV1_PPSERR_FRAME_SIZE_HEIGHT 0x00002002
|
||||
#define AV1_PPSERR_SEEN_FRAME_HEADER 0x00002003
|
||||
#define AV1_PPSERR_REF_VALID 0x00002007
|
||||
#define AV1_PPSERR_LAST_ORDER_HINT 0x0000200B
|
||||
#define AV1_PPSERR_GOLD_ORDER_HINT 0x0000200C
|
||||
#define AV1_PPSERR_CODED_LOSSLESS_DELTA_Q 0x0000200E
|
||||
#define AV1_PPSERR_FILM_GRAIN_PARAM_REF_IDX 0x0000200F
|
||||
#define AV1_PPSERR_SEQ_CHANGE_BIT_DEPTH 0x00002010
|
||||
#define AV1_PPSERR_SEQ_CHANGE_PROFILE 0x00002012
|
||||
#define AV1_PPSERR_SEQ_CHANGE_DETECTED_INTER 0x00002013
|
||||
#define AV1_PPSERR_NUM_Y_POINTS 0x00002014
|
||||
#define AV1_PPSERR_POINT_Y_VALUE 0x00002015
|
||||
#define AV1_PPSERR_NUM_CB_POINTS 0x00002016
|
||||
#define AV1_PPSERR_POINT_CB_VALUE 0x00002017
|
||||
#define AV1_PPSERR_NUM_CR_POINTS 0x00002018
|
||||
#define AV1_PPSERR_POINT_CR_VALUE 0x00002019
|
||||
#define AV1_PPSERR_SUBSAMPLING_FORMAT 0x0000201A
|
||||
#define AV1_FRAMEERR_TILE_START_END_PRESENT 0x00003001
|
||||
#define AV1_FRAMEERR_SHOW_EXISING_FRAME 0x00003002
|
||||
#define AV1_TGERR_NUM_TILES_ZERO 0x00004001
|
||||
#define AV1_TGERR_START_NOT_TILE_NUM 0x00004002
|
||||
#define AV1_TGERR_END_LESS_THAN_TG_START 0x00004003
|
||||
#define AV1_TGERR_TILE_SIZE_GREATER_THAN_32M 0x00004004
|
||||
#define AV1_SPECERR_OVER_MAX_H_SIZE 0x00005001
|
||||
#define AV1_SPECERR_OVER_MAX_V_SIZE 0x00005002
|
||||
#define AV1_SPECERR_OVER_MAX_TILE_COLS 0x00005004
|
||||
#define AV1_SPECERR_OVER_MAX_TILE_ROWS 0x00005005
|
||||
#define AV1_SPECERR_OVER_TILE_SIZE 0x00005006
|
||||
#define AV1_SPECERR_OVER_NUMTILES_GT_MAX_TILES 0x00005007
|
||||
#define AV1_ETCERR_OBU_HEADER 0x00006001
|
||||
#define AV1_ETCERR_OBU_SIZE 0x00006003
|
||||
#define AV1_ETCERR_OVERCONSUME 0x00006004
|
||||
#define AV1_ETCERR_NOT_SUPPORTED_FEATURE 0x00006005
|
||||
#define AV1_ETCERR_RESILIENCE_FAIL 0x00006006
|
||||
|
||||
// VP9
|
||||
#define VP9_PICERR_FRAME_MARKER 0x00001000
|
||||
#define VP9_PICERR_PROFILE 0x00001001
|
||||
#define VP9_PICERR_SYNC_CODE 0x00001002
|
||||
#define VP9_PICERR_PROFILE_COLOR_SAMPLE 0x00001003
|
||||
#define VP9_PICERR_FRAME_SIZE 0x00001004
|
||||
#define VP9_PICERR_SEGMENT 0x00001005
|
||||
#define VP9_PICERR_TILE 0x00001006
|
||||
#define VP9_PICERR_PROFILE_COMP_MISMATCH_WITH_REF 0x00001007
|
||||
#define VP9_PICERR_COMP_DAT_OVER_CS 0x00001008
|
||||
#define VP9_PICERR_COMP_TRAILING_BIT_ERR 0x00001009
|
||||
#define VP9_PICERR_MARKER 0x0000100A
|
||||
#define VP9_PICERR_NOT_EXIST_REF_FRAME 0x0000100B
|
||||
#define VP9_PICERR_UNINIT_CTX 0x0000100C
|
||||
#define VP9_PICERR_FRAME_SIZE_LIMIT_BY_REF 0x0000100D
|
||||
#define VP9_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000
|
||||
#define VP9_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001
|
||||
#define VP9_SPECERR_OVER_CHROMA_FORMAT 0x00004002
|
||||
#define VP9_SPECERR_OVER_BIT_DEPTH 0x00004003
|
||||
#define VP9_ETCERR_INIT_KEY_FRAME_NOT_FOUND 0x00005000
|
||||
#define VP9_ETCERR_FORBIDDEN_BS_MODE 0x00005004
|
||||
#define VP9_ETCERR_SPP_OVER_CS_AU 0x00005005
|
||||
|
||||
// AVS2
|
||||
#define AVS2_SPSERR_PROFILE_ID 0x00001000
|
||||
#define AVS2_SPSERR_LEVEL_ID 0x00001001
|
||||
#define AVS2_SPSERR_HORIZONTAL_SIZE 0x00001002
|
||||
#define AVS2_SPSERR_VERTICAL_SIZE 0x00001003
|
||||
#define AVS2_SPSERR_CHROMA_FORMAT 0x00001004
|
||||
#define AVS2_SPSERR_SAMPLE_PRECISION 0x00001005
|
||||
#define AVS2_SPSERR_ENCODING_PRECISION 0x00001006
|
||||
#define AVS2_SPSERR_LCU_SIZE 0x00001007
|
||||
#define AVS2_SPSERR_WEIGHT_QUANT_MATRIX 0x00001008
|
||||
#define AVS2_SPSERR_NUM_OF_RCS 0x00001009
|
||||
#define AVS2_SPSERR_REFERENCE_CONFIGURATION_SET 0x0000100A
|
||||
#define AVS2_SPSERR_OUTPUT_REORDER_DELAY 0x0000100B
|
||||
#define AVS2_PPSERR_BBV_DELAY 0x00002000
|
||||
#define AVS2_PPSERR_TIME_CODE 0x00002001
|
||||
#define AVS2_PPSERR_DECODE_ORDER_INDEX 0x00002002
|
||||
#define AVS2_PPSERR_TEMPORAL_ID 0x00002003
|
||||
#define AVS2_PPSERR_PICTURE_OUTPUT_DELAY 0x00002004
|
||||
#define AVS2_PPSERR_RCS_INDEX 0x00002005
|
||||
#define AVS2_PPSERR_REFERENCE_CONFIGURATION_SET 0x00002006
|
||||
#define AVS2_PPSERR_BBV_CHECK_TIMES 0x00002007
|
||||
#define AVS2_PPSERR_PICTURE_QP 0x00002008
|
||||
#define AVS2_PPSERR_ALPHA_C_OFFSET 0x00002009
|
||||
#define AVS2_PPSERR_BETA_OFFSET 0x0000200A
|
||||
#define AVS2_PPSERR_CHROMA_QUANT_PARAM_DELTA_CB 0x0000200B
|
||||
#define AVS2_PPSERR_CHROMA_QUANT_PARAM_DELTA_CR 0x0000200C
|
||||
#define AVS2_PPSERR_WEIGHT_QUANT_PARAM_DELTA1 0x0000200D
|
||||
#define AVS2_PPSERR_WEIGHT_QUANT_PARAM_DELTA2 0x0000200E
|
||||
#define AVS2_PPSERR_PICTURE_CODING_TYPE 0x0000200F
|
||||
#define AVS2_PPSERR_ALF_FILTER_NUM_MINUS1 0x00002010
|
||||
#define AVS2_PPSERR_ALF_REGION_DISTANCE 0x00002011
|
||||
#define AVS2_PPSERR_ALF_COEFF_LUMA 0x00002012
|
||||
#define AVS2_PPSERR_ALF_COEFF_CHROMA_CB 0x00002013
|
||||
#define AVS2_PPSERR_ALF_COEFF_CHROMA_CR 0x00002014
|
||||
#define AVS2_SHERR_SLICE_VERTICAL_POSITION 0x00003000
|
||||
#define AVS2_SHERR_SLICE_VERTICAL_POSITION_EXTENSION 0x00003001
|
||||
#define AVS2_SHERR_SLICE_HORIZONTAL_POSITION 0x00003002
|
||||
#define AVS2_SHERR_SLICE_HORIZONTAL_POSITION_EXTENSION 0x00003003
|
||||
#define AVS2_SHERR_FIXED_SLICE_QP 0x00003004
|
||||
#define AVS2_SHERR_SLICE_QP 0x00003005
|
||||
#define AVS2_SHERR_SLICE_SAO_ENABLE_FLAG 0x00003006
|
||||
#define AVS2_SHERR_AEC_BYTE_ALIGNMENT_BIT 0x00003007
|
||||
#define AVS2_SHERR_STREAM_END 0x00003008
|
||||
#define AVS2_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000
|
||||
#define AVS2_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001
|
||||
#define AVS2_SPECERR_OVER_CHROMA_FORMAT 0x00004002
|
||||
#define AVS2_SPECERR_OVER_BIT_DEPTH 0x00004003
|
||||
#define AVS2_SPECERR_OVER_REF_TEMPORAL_ID 0x00004004
|
||||
#define AVS2_ETCERR_SPS_NOT_FOUND 0x00005000
|
||||
#define AVS2_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001
|
||||
#define AVS2_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002
|
||||
#define AVS2_ETCERR_PPS_ERROR 0x00005003
|
||||
#define AVS2_ETCERR_SLICE_NUM_OVERFLOW 0x00005004
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 WARNING ON DECODER (WARN_INFO) */
|
||||
/************************************************************************/
|
||||
// HEVC
|
||||
#define HEVC_SPSWARN_MAX_SUB_LAYERS_MINUS1 0x00000001
|
||||
#define HEVC_SPSWARN_GENERAL_RESERVED_ZERO_44BITS 0x00000002
|
||||
#define HEVC_SPSWARN_RESERVED_ZERO_2BITS 0x00000004
|
||||
#define HEVC_SPSWARN_SUB_LAYER_RESERVED_ZERO_44BITS 0x00000008
|
||||
#define HEVC_SPSWARN_GENERAL_LEVEL_IDC 0x00000010
|
||||
#define HEVC_SPSWARN_SPS_MAX_DEC_PIC_BUFFERING_VALUE_OVER 0x00000020
|
||||
#define HEVC_SPSWARN_RBSP_TRAILING_BITS 0x00000040
|
||||
#define HEVC_SPSWARN_ST_RPS_UE_ERROR 0x00000080
|
||||
#define HEVC_SPSWARN_EXTENSION_FLAG 0x01000000
|
||||
#define HEVC_SPSWARN_REPLACED_WITH_PREV_SPS 0x02000000
|
||||
#define HEVC_PPSWARN_RBSP_TRAILING_BITS 0x00000100
|
||||
#define HEVC_PPSWARN_REPLACED_WITH_PREV_PPS 0x00000200
|
||||
#define HEVC_SHWARN_FIRST_SLICE_SEGMENT_IN_PIC_FLAG 0x00001000
|
||||
#define HEVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG 0x00002000
|
||||
#define HEVC_SHWARN_PIC_OUTPUT_FLAG 0x00004000
|
||||
#define HEVC_SHWARN_DUPLICATED_SLICE_SEGMENT 0x00008000
|
||||
#define HEVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000
|
||||
#define HEVC_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000
|
||||
#define HEVC_ETCWARN_WRONG_TEMPORAL_ID 0x00040000
|
||||
#define HEVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000
|
||||
#define HEVC_SPECWARN_OVER_PROFILE 0x00100000
|
||||
#define HEVC_SPECWARN_OVER_LEVEL 0x00200000
|
||||
#define HEVC_PRESWARN_PARSING_ERR 0x04000000
|
||||
#define HEVC_PRESWARN_MVD_OUT_OF_RANGE 0x08000000
|
||||
#define HEVC_PRESWARN_CU_QP_DELTA_VAL_OUT_OF_RANGE 0x09000000
|
||||
#define HEVC_PRESWARN_COEFF_LEVEL_REMAINING_OUT_OF_RANGE 0x0A000000
|
||||
#define HEVC_PRESWARN_PCM_ERR 0x0B000000
|
||||
#define HEVC_PRESWARN_OVERCONSUME 0x0C000000
|
||||
#define HEVC_PRESWARN_END_OF_SUBSET_ONE_BIT_ERR 0x10000000
|
||||
#define HEVC_PRESWARN_END_OF_SLICE_SEGMENT_FLAG 0x20000000
|
||||
|
||||
// AVC
|
||||
#define AVC_SPSWARN_RESERVED_ZERO_2BITS 0x00000004
|
||||
#define AVC_SPSWARN_GENERAL_LEVEL_IDC 0x00000010
|
||||
#define AVC_SPSWARN_RBSP_TRAILING_BITS 0x00000040
|
||||
#define AVC_PPSWARN_RBSP_TRAILING_BITS 0x00000100
|
||||
#define AVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG 0x00002000
|
||||
#define AVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000
|
||||
#define AVC_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000
|
||||
#define AVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000
|
||||
#define AVC_SPECWARN_OVER_PROFILE 0x00100000
|
||||
#define AVC_SPECWARN_OVER_LEVEL 0x00200000
|
||||
#define AVC_PRESWARN_MVD_RANGE_OUT 0x00400000
|
||||
#define AVC_PRESWARN_MB_QPD_RANGE_OUT 0x00500000
|
||||
#define AVC_PRESWARN_COEFF_RANGE_OUT 0x00600000
|
||||
#define AVC_PRESWARN_MV_RANGE_OUT 0x00700000
|
||||
#define AVC_PRESWARN_MB_SKIP_RUN_RANGE_OUT 0x00800000
|
||||
#define AVC_PRESWARN_MB_TYPE_RANGE_OUT 0x00900000
|
||||
#define AVC_PRESWARN_SUB_MB_TYPE_RANGE_OUT 0x00A00000
|
||||
#define AVC_PRESWARN_CBP_RANGE_OUT 0x00B00000
|
||||
#define AVC_PRESWARN_INTRA_CHROMA_PRED_MODE_RANGE_OUT 0x00C00000
|
||||
#define AVC_PRESWARN_REF_IDX_RANGE_OUT 0x00D00000
|
||||
#define AVC_PRESWARN_COEFF_TOKEN_RANGE_OUT 0x00E00000
|
||||
#define AVC_PRESWARN_TOTAL_ZERO_RANGE_OUT 0x00F00000
|
||||
#define AVC_PRESWARN_RUN_BEFORE_RANGE_OUT 0x01000000
|
||||
#define AVC_PRESWARN_OVERCONSUME 0x01100000
|
||||
#define AVC_PRESWARN_MISSING_SLICE 0x01200000
|
||||
|
||||
// AV1
|
||||
#define AV1_SPSWARN_OBU_EXTENSION_FLAG_ZERO 0x00001000
|
||||
#define AV1_SPSWARN_DUPLICATE_OPERATING_POINT_IDX 0x00001001
|
||||
#define AV1_SPSWARN_MC_IDENTIY_SUBSAMPLING_X 0x00001002
|
||||
#define AV1_PPSWARN_MC_IDENTIY_SUBSAMPLING_Y 0x00001003
|
||||
#define AV1_SPSWARN_NUM_UNITS_IN_DISPLAY_TICK 0x00001004
|
||||
#define AV1_SPSWARN_TIME_SCALE_ZERO 0x00001005
|
||||
#define AV1_SPSWARN_NUM_TICKS_PER_PICTURE 0x00001006
|
||||
#define AV1_PPSWARN_TILE_WIDTH 0x00002001
|
||||
#define AV1_PPSWARN_TILE_HEIGHT 0x00002002
|
||||
#define AV1_PPSWARN_SHOW_EXISTING_KEY_FRAME_OUTPUT 0x00002004
|
||||
#define AV1_PPSWARN_DIFF_FRAME_ID 0x00002008
|
||||
#define AV1_PPSWARN_CURRENT_FRAME_ID 0x00002010
|
||||
#define AV1_PPSWARN_REFRESH_FRAME_FLAGS 0x00002020
|
||||
#define AV1_PPSWARN_DISPLAY_ID 0x00002040
|
||||
#define AV1_PPSWARN_PREV_FRAME_SHOWABLE_FLAG_ZERO 0x00002080
|
||||
#define AV1_PPSWARN_EXPECTED_FRAME_ID 0x00002100
|
||||
#define AV1_SPECWARN_OVER_MAX_TILE_AREA_SB 0x00005000
|
||||
#define AV1_SPECWARN_OVER_MAX_PIC_SIZE 0x00005001
|
||||
#define AV1_ETCWARN_OBU_EXTENSION_FLAG 0x00006000
|
||||
#define AV1_TGWARN_TRAIL_BIT_POS 0x00400000
|
||||
#define AV1_TGWARN_TRAIL_PAD_BIT 0x00800000
|
||||
#define AV1_TGWARN_SYM_MAX_OVER 0x01000000
|
||||
#define AV1_TGWARN_EXP_GOLB_OVER 0x02000000
|
||||
#define AV1_TGWARN_MV_NOT_VALID 0x04000000
|
||||
|
||||
// VP9
|
||||
#define VP9_PICWARN_COLOR_SPACE_MISMATCH_WITH_REF 0x00001000
|
||||
#define VP9_PRESWARN_OVERCONSUME 0x00400000
|
||||
#define VP9_PRESWARN_TRAILING_BITS 0x00800000
|
||||
#define VP9_PRESWARN_MARKER 0x01000000
|
||||
#define VP9_PRESWARN_MV_RANGE_OVER 0x02000000
|
||||
#define VP9_PRESWARN_MISIZE_SEG_LVL_ACTIVE 0x04000000
|
||||
|
||||
// AVS2
|
||||
#define AVS2_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000
|
||||
#define AVS2_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000
|
||||
#define AVS2_ETCWARN_WRONG_TEMPORAL_ID 0x00040000
|
||||
#define AVS2_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000
|
||||
#define AVS2_ETCWARN_REF_WRONG_TEMPORAL_ID 0x00080001
|
||||
#define AVS2_ETCWARN_SPS_ERROR 0x00080002
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 ERROR ON ENCODER (ERR_INFO) */
|
||||
/************************************************************************/
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 WARNING ON ENCODER (WARN_INFO) */
|
||||
/************************************************************************/
|
||||
#define WAVE5_ETCWARN_FORCED_SPLIT_BY_CU8X8 0x000000001
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 debug info (PRI_REASON) */
|
||||
/************************************************************************/
|
||||
#define WAVE5_DEC_VCORE_VCE_HANGUP 0x0001
|
||||
#define WAVE5_DEC_VCORE_UNDETECTED_SYNTAX_ERR 0x0002
|
||||
#define WAVE5_DEC_VCORE_MIB_BUSY 0x0003
|
||||
#define WAVE5_DEC_VCORE_VLC_BUSY 0x0004
|
||||
|
||||
#endif /* ERROR_CODE_H_INCLUDED */
|
||||
94
drivers/media/platform/chips-media/wave5/wave5.h
Normal file
94
drivers/media/platform/chips-media/wave5/wave5.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - wave5 backend definitions
|
||||
*
|
||||
* Copyright (C) 2021 CHIPS&MEDIA INC
|
||||
*/
|
||||
|
||||
#ifndef __WAVE5_FUNCTION_H__
|
||||
#define __WAVE5_FUNCTION_H__
|
||||
|
||||
#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h) (ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8))
|
||||
#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h) (ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4))
|
||||
|
||||
#define BSOPTION_ENABLE_EXPLICIT_END BIT(0)
|
||||
|
||||
#define WTL_RIGHT_JUSTIFIED 0
|
||||
#define WTL_LEFT_JUSTIFIED 1
|
||||
#define WTL_PIXEL_8BIT 0
|
||||
#define WTL_PIXEL_16BIT 1
|
||||
#define WTL_PIXEL_32BIT 2
|
||||
|
||||
/* Mirror & rotation modes of the PRP (pre-processing) module */
|
||||
#define NONE_ROTATE 0x0
|
||||
#define ROT_CLOCKWISE_90 0x3
|
||||
#define ROT_CLOCKWISE_180 0x5
|
||||
#define ROT_CLOCKWISE_270 0x7
|
||||
#define MIR_HOR_FLIP 0x11
|
||||
#define MIR_VER_FLIP 0x9
|
||||
#define MIR_HOR_VER_FLIP (MIR_HOR_FLIP | MIR_VER_FLIP)
|
||||
|
||||
bool wave5_vpu_is_init(struct vpu_device *vpu_dev);
|
||||
|
||||
unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev);
|
||||
|
||||
void wave5_bit_issue_command(struct vpu_instance *inst, u32 cmd);
|
||||
|
||||
int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision);
|
||||
|
||||
int wave5_vpu_init(struct device *dev, u8 *fw, size_t size);
|
||||
|
||||
int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode);
|
||||
|
||||
int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);
|
||||
|
||||
int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);
|
||||
|
||||
int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,
|
||||
struct frame_buffer *fb_arr, enum tiled_map_type map_type,
|
||||
unsigned int count);
|
||||
|
||||
int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size);
|
||||
|
||||
int wave5_vpu_dec_init_seq(struct vpu_instance *inst);
|
||||
|
||||
int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);
|
||||
|
||||
int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res);
|
||||
|
||||
int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);
|
||||
|
||||
int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);
|
||||
|
||||
int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);
|
||||
|
||||
int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);
|
||||
|
||||
int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);
|
||||
|
||||
dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst);
|
||||
|
||||
int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);
|
||||
|
||||
/***< WAVE5 encoder >******/
|
||||
|
||||
int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,
|
||||
struct enc_open_param *open_param);
|
||||
|
||||
int wave5_vpu_enc_init_seq(struct vpu_instance *inst);
|
||||
|
||||
int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);
|
||||
|
||||
int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,
|
||||
struct frame_buffer *fb_arr, enum tiled_map_type map_type,
|
||||
unsigned int count);
|
||||
|
||||
int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);
|
||||
|
||||
int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);
|
||||
|
||||
int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);
|
||||
|
||||
int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);
|
||||
|
||||
#endif /* __WAVE5_FUNCTION_H__ */
|
||||
Loading…
Add table
Reference in a new issue