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drm/amdgpu/gfx10: add placeholder for navi12 golden settings

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Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaojie Yuan 2019-06-11 11:16:54 +08:00 • committed by Alex Deucher
parent 92c123aec1
commit 716e9bb099
1 changed files with 13 additions and 0 deletions
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13
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -174,6 +174,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
/* Pending on emulation bring up */
};
static const struct soc15_reg_golden golden_settings_gc_10_1_nv12[] =
{
/* Pending on emulation bring up */
};
#define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
(SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@ -323,6 +328,14 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_10_1_nv14,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
break;
case CHIP_NAVI12:
soc15_program_register_sequence(adev,
golden_settings_gc_10_1,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
soc15_program_register_sequence(adev,
golden_settings_gc_10_1_nv12,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv12));
break;
default:
break;
}