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ARC: boot log: eliminate struct cpuinfo_arc #1: mm
This is first step in eliminating struct cpuinfo_arc[NR_CPUS] Back when we had just ARCompact ISA, the idea was to read/bit-fiddle the BCRs once and and cache decoded information in a global struct ready to use. With ARCv2 it was modified to contained abstract / ISA agnostic information. However with ARCv3 there 's too much disparity to abstract in common structures. So drop the entire decode once and store paradigm. Afterall there's only 2 users of this machinery anyways: boot printing and cat /proc/cpuinfo. None is performance critical to warrant locking away resident memory per cpu. This patch is first step in that direction - decouples struct cpuinfo_arc_mmu from global struct cpuinfo_arc - mmu code still has a trimmed down static version of struct cpuinfo_arc_mmu to cache information needed in performance critical code such as tlb flush routines - folds read_decode_mmu_bcr() into arc_mmu_mumbojumbo() - setup_processor() directly calls arc_mmu_init() and not via arc_cpu_init() Tested-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202308151213.qKZPMiyz-lkp@intel.com/ Signed-off-by: Vineet Gupta <vgupta@kernel.org>
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parent
1918693ff1
commit
72d861f2d2
4 changed files with 58 additions and 67 deletions
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@ -185,6 +185,27 @@ struct bcr_uarch_build_arcv2 {
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#endif
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};
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struct bcr_mmu_3 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
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u_itlb:4, u_dtlb:4;
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#else
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unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
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ways:4, ver:8;
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#endif
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};
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struct bcr_mmu_4 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
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n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
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#else
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/* DTLB ITLB JES JE JA */
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unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
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pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
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#endif
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};
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struct bcr_mpy {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
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@ -307,11 +328,6 @@ struct bcr_generic {
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* Generic structures to hold build configuration used at runtime
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*/
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struct cpuinfo_arc_mmu {
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unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
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unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
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};
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struct cpuinfo_arc_cache {
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unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
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};
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@ -326,7 +342,6 @@ struct cpuinfo_arc_ccm {
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struct cpuinfo_arc {
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struct cpuinfo_arc_cache icache, dcache, slc;
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struct cpuinfo_arc_mmu mmu;
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struct cpuinfo_arc_bpu bpu;
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struct bcr_identity core;
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struct bcr_isa_arcv2 isa;
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@ -36,7 +36,6 @@ long __init arc_get_mem_sz(void);
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extern void arc_mmu_init(void);
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extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
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extern void read_decode_mmu_bcr(void);
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extern void arc_cache_init(void);
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extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
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@ -186,7 +186,6 @@ static void read_arc_build_cfg_regs(void)
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/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
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read_decode_ccm_bcr(cpu);
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read_decode_mmu_bcr();
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read_decode_cache_bcr();
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if (is_isa_arcompact()) {
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@ -256,7 +255,7 @@ static void read_arc_build_cfg_regs(void)
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cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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/* there's no direct way to distinguish 750 vs. 770 */
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if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
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if (unlikely(cpu->core.family < 0x34))
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cpu->name = "ARC750";
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} else {
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cpu->isa = isa;
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@ -463,6 +462,7 @@ void setup_processor(void)
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arc_init_IRQ();
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pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
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pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str)));
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arc_mmu_init();
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arc_cache_init();
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@ -18,7 +18,9 @@
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/* A copy of the ASID from the PID reg is kept in asid_cache */
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DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
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static int __read_mostly pae_exists;
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static struct cpuinfo_arc_mmu {
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unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways;
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} mmuinfo;
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/*
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* Utility Routine to erase a J-TLB entry
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@ -131,7 +133,7 @@ static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
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noinline void local_flush_tlb_all(void)
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{
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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struct cpuinfo_arc_mmu *mmu = &mmuinfo;
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unsigned long flags;
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unsigned int entry;
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int num_tlb = mmu->sets * mmu->ways;
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@ -560,89 +562,64 @@ void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
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* the cpuinfo structure for later use.
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* No Validation is done here, simply read/convert the BCRs
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*/
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void read_decode_mmu_bcr(void)
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char *arc_mmu_mumbojumbo(int c, char *buf, int len)
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{
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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unsigned int tmp;
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struct bcr_mmu_3 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
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u_itlb:4, u_dtlb:4;
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#else
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unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
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ways:4, ver:8;
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#endif
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} *mmu3;
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struct cpuinfo_arc_mmu *mmu = &mmuinfo;
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unsigned int bcr, u_dtlb, u_itlb, sasid;
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struct bcr_mmu_3 *mmu3;
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struct bcr_mmu_4 *mmu4;
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char super_pg[64] = "";
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int n = 0;
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struct bcr_mmu_4 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
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n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
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#else
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/* DTLB ITLB JES JE JA */
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unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
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pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
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#endif
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} *mmu4;
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tmp = read_aux_reg(ARC_REG_MMU_BCR);
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mmu->ver = (tmp >> 24);
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bcr = read_aux_reg(ARC_REG_MMU_BCR);
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mmu->ver = (bcr >> 24);
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if (is_isa_arcompact() && mmu->ver == 3) {
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mmu3 = (struct bcr_mmu_3 *)&tmp;
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mmu3 = (struct bcr_mmu_3 *)&bcr;
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mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
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mmu->sets = 1 << mmu3->sets;
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mmu->ways = 1 << mmu3->ways;
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mmu->u_dtlb = mmu3->u_dtlb;
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mmu->u_itlb = mmu3->u_itlb;
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mmu->sasid = mmu3->sasid;
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u_dtlb = mmu3->u_dtlb;
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u_itlb = mmu3->u_itlb;
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sasid = mmu3->sasid;
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} else {
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mmu4 = (struct bcr_mmu_4 *)&tmp;
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mmu4 = (struct bcr_mmu_4 *)&bcr;
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mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
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mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
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mmu->sets = 64 << mmu4->n_entry;
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mmu->ways = mmu4->n_ways * 2;
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mmu->u_dtlb = mmu4->u_dtlb * 4;
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mmu->u_itlb = mmu4->u_itlb * 4;
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mmu->sasid = mmu4->sasid;
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pae_exists = mmu->pae = mmu4->pae;
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u_dtlb = mmu4->u_dtlb * 4;
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u_itlb = mmu4->u_itlb * 4;
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sasid = mmu4->sasid;
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mmu->pae = mmu4->pae;
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}
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}
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char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
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{
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int n = 0;
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struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
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char super_pg[64] = "";
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if (p_mmu->s_pg_sz_m)
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scnprintf(super_pg, 64, "%dM Super Page %s",
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p_mmu->s_pg_sz_m,
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IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
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if (mmu->s_pg_sz_m)
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scnprintf(super_pg, 64, "/%dM%s",
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mmu->s_pg_sz_m,
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IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) ? " (THP enabled)":"");
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n += scnprintf(buf + n, len - n,
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"MMU [v%x]\t: %dk PAGE, %s, swalk %d lvl, JTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
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p_mmu->ver, p_mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS,
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p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
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p_mmu->u_dtlb, p_mmu->u_itlb,
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IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
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"MMU [v%x]\t: %dk%s, swalk %d lvl, JTLB %dx%d, uDTLB %d, uITLB %d%s%s%s\n",
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mmu->ver, mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS,
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mmu->sets, mmu->ways,
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u_dtlb, u_itlb,
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IS_AVAIL1(sasid, ", SASID"),
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IS_AVAIL2(mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
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return buf;
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}
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int pae40_exist_but_not_enab(void)
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{
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return pae_exists && !is_pae40_enabled();
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return mmuinfo.pae && !is_pae40_enabled();
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}
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void arc_mmu_init(void)
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{
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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char str[256];
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struct cpuinfo_arc_mmu *mmu = &mmuinfo;
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int compat = 0;
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pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
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/*
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* Can't be done in processor.h due to header include dependencies
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*/
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@ -719,7 +696,7 @@ volatile int dup_pd_silent; /* Be silent abt it or complain (default) */
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void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
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struct pt_regs *regs)
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{
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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struct cpuinfo_arc_mmu *mmu = &mmuinfo;
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unsigned long flags;
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int set, n_ways = mmu->ways;
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