mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-07-23 07:12:09 +00:00
mfd: Move to the new db500 PRCMU API
Now that we have a shared API between the DB8500 and DB5500 PRCMU's, switch to using this neutral API instead. We delete the parts of db8500-prcmu.h that is now PRCMU-neutral, and calls will be diverted to respective driver. Common registers are in dbx500-prcmu-regs.h and common accessors and defines in <linux/mfd/dbx500-prcmu.h> This way we get a a lot more abstraction and code reuse. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Mattias Nilsson
Samuel Ortiz
parent
fea799e3d3
commit
73180f85f4
10 changed files with 247 additions and 492 deletions
|
|
@ -11,7 +11,6 @@
|
|||
#define __MFD_DB8500_PRCMU_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
|
||||
|
||||
|
|
@ -133,7 +132,7 @@ enum ap_pwrst {
|
|||
* @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
|
||||
*/
|
||||
enum ap_pwrst_trans {
|
||||
NO_TRANSITION = 0x00,
|
||||
PRCMU_AP_NO_CHANGE = 0x00,
|
||||
APEXECUTE_TO_APSLEEP = 0x01,
|
||||
APIDLE_TO_APSLEEP = 0x02, /* To be removed */
|
||||
PRCMU_AP_SLEEP = 0x01,
|
||||
|
|
@ -145,54 +144,6 @@ enum ap_pwrst_trans {
|
|||
PRCMU_AP_DEEP_IDLE = 0x07,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ddr_pwrst - DDR power states definition
|
||||
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
|
||||
* @DDR_PWR_STATE_ON:
|
||||
* @DDR_PWR_STATE_OFFLOWLAT:
|
||||
* @DDR_PWR_STATE_OFFHIGHLAT:
|
||||
*/
|
||||
enum ddr_pwrst {
|
||||
DDR_PWR_STATE_UNCHANGED = 0x00,
|
||||
DDR_PWR_STATE_ON = 0x01,
|
||||
DDR_PWR_STATE_OFFLOWLAT = 0x02,
|
||||
DDR_PWR_STATE_OFFHIGHLAT = 0x03
|
||||
};
|
||||
|
||||
/**
|
||||
* enum arm_opp - ARM OPP states definition
|
||||
* @ARM_OPP_INIT:
|
||||
* @ARM_NO_CHANGE: The ARM operating point is unchanged
|
||||
* @ARM_100_OPP: The new ARM operating point is arm100opp
|
||||
* @ARM_50_OPP: The new ARM operating point is arm50opp
|
||||
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
|
||||
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
|
||||
* @ARM_EXTCLK: The new ARM operating point is armExtClk
|
||||
*/
|
||||
enum arm_opp {
|
||||
ARM_OPP_INIT = 0x00,
|
||||
ARM_NO_CHANGE = 0x01,
|
||||
ARM_100_OPP = 0x02,
|
||||
ARM_50_OPP = 0x03,
|
||||
ARM_MAX_OPP = 0x04,
|
||||
ARM_MAX_FREQ100OPP = 0x05,
|
||||
ARM_EXTCLK = 0x07
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ape_opp - APE OPP states definition
|
||||
* @APE_OPP_INIT:
|
||||
* @APE_NO_CHANGE: The APE operating point is unchanged
|
||||
* @APE_100_OPP: The new APE operating point is ape100opp
|
||||
* @APE_50_OPP: 50%
|
||||
*/
|
||||
enum ape_opp {
|
||||
APE_OPP_INIT = 0x00,
|
||||
APE_NO_CHANGE = 0x01,
|
||||
APE_100_OPP = 0x02,
|
||||
APE_50_OPP = 0x03
|
||||
};
|
||||
|
||||
/**
|
||||
* enum hw_acc_state - State definition for hardware accelerator
|
||||
* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
|
||||
|
|
@ -469,26 +420,6 @@ enum auto_enable {
|
|||
|
||||
/* End of file previously known as prcmu-fw-defs_v1.h */
|
||||
|
||||
/* PRCMU Wakeup defines */
|
||||
enum prcmu_wakeup_index {
|
||||
PRCMU_WAKEUP_INDEX_RTC,
|
||||
PRCMU_WAKEUP_INDEX_RTT0,
|
||||
PRCMU_WAKEUP_INDEX_RTT1,
|
||||
PRCMU_WAKEUP_INDEX_HSI0,
|
||||
PRCMU_WAKEUP_INDEX_HSI1,
|
||||
PRCMU_WAKEUP_INDEX_USB,
|
||||
PRCMU_WAKEUP_INDEX_ABB,
|
||||
PRCMU_WAKEUP_INDEX_ABB_FIFO,
|
||||
PRCMU_WAKEUP_INDEX_ARM,
|
||||
NUM_PRCMU_WAKEUP_INDICES
|
||||
};
|
||||
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
|
||||
|
||||
/* PRCMU QoS APE OPP class */
|
||||
#define PRCMU_QOS_APE_OPP 1
|
||||
#define PRCMU_QOS_DDR_OPP 2
|
||||
#define PRCMU_QOS_DEFAULT_VALUE -1
|
||||
|
||||
/**
|
||||
* enum hw_acc_dev - enum for hw accelerators
|
||||
* @HW_ACC_SVAMMDSP: for SVAMMDSP
|
||||
|
|
@ -526,64 +457,6 @@ enum hw_acc_dev {
|
|||
NUM_HW_ACC
|
||||
};
|
||||
|
||||
/*
|
||||
* Ids for all EPODs (power domains)
|
||||
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
|
||||
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
|
||||
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
|
||||
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
|
||||
* - EPOD_ID_SGA: power domain for SGA
|
||||
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
|
||||
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
|
||||
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
|
||||
* - NUM_EPOD_ID: number of power domains
|
||||
*/
|
||||
#define EPOD_ID_SVAMMDSP 0
|
||||
#define EPOD_ID_SVAPIPE 1
|
||||
#define EPOD_ID_SIAMMDSP 2
|
||||
#define EPOD_ID_SIAPIPE 3
|
||||
#define EPOD_ID_SGA 4
|
||||
#define EPOD_ID_B2R2_MCDE 5
|
||||
#define EPOD_ID_ESRAM12 6
|
||||
#define EPOD_ID_ESRAM34 7
|
||||
#define NUM_EPOD_ID 8
|
||||
|
||||
/*
|
||||
* state definition for EPOD (power domain)
|
||||
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
|
||||
* - EPOD_STATE_OFF: The EPOD is switched off
|
||||
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
|
||||
* retention
|
||||
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
|
||||
* - EPOD_STATE_ON: Same as above, but with clock enabled
|
||||
*/
|
||||
#define EPOD_STATE_NO_CHANGE 0x00
|
||||
#define EPOD_STATE_OFF 0x01
|
||||
#define EPOD_STATE_RAMRET 0x02
|
||||
#define EPOD_STATE_ON_CLK_OFF 0x03
|
||||
#define EPOD_STATE_ON 0x04
|
||||
|
||||
/*
|
||||
* CLKOUT sources
|
||||
*/
|
||||
#define PRCMU_CLKSRC_CLK38M 0x00
|
||||
#define PRCMU_CLKSRC_ACLK 0x01
|
||||
#define PRCMU_CLKSRC_SYSCLK 0x02
|
||||
#define PRCMU_CLKSRC_LCDCLK 0x03
|
||||
#define PRCMU_CLKSRC_SDMMCCLK 0x04
|
||||
#define PRCMU_CLKSRC_TVCLK 0x05
|
||||
#define PRCMU_CLKSRC_TIMCLK 0x06
|
||||
#define PRCMU_CLKSRC_CLK009 0x07
|
||||
/* These are only valid for CLKOUT1: */
|
||||
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
|
||||
#define PRCMU_CLKSRC_I2CCLK 0x41
|
||||
#define PRCMU_CLKSRC_MSP02CLK 0x42
|
||||
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
|
||||
#define PRCMU_CLKSRC_HSIRXCLK 0x44
|
||||
#define PRCMU_CLKSRC_HSITXCLK 0x45
|
||||
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
|
||||
#define PRCMU_CLKSRC_HDMICLK 0x47
|
||||
|
||||
/*
|
||||
* Definitions for autonomous power management configuration.
|
||||
*/
|
||||
|
|
@ -620,88 +493,12 @@ struct prcmu_auto_pm_config {
|
|||
u8 sva_policy;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ddr_opp - DDR OPP states definition
|
||||
* @DDR_100_OPP: The new DDR operating point is ddr100opp
|
||||
* @DDR_50_OPP: The new DDR operating point is ddr50opp
|
||||
* @DDR_25_OPP: The new DDR operating point is ddr25opp
|
||||
*/
|
||||
enum ddr_opp {
|
||||
DDR_100_OPP = 0x00,
|
||||
DDR_50_OPP = 0x01,
|
||||
DDR_25_OPP = 0x02,
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock identifiers.
|
||||
*/
|
||||
enum prcmu_clock {
|
||||
PRCMU_SGACLK,
|
||||
PRCMU_UARTCLK,
|
||||
PRCMU_MSP02CLK,
|
||||
PRCMU_MSP1CLK,
|
||||
PRCMU_I2CCLK,
|
||||
PRCMU_SDMMCCLK,
|
||||
PRCMU_SLIMCLK,
|
||||
PRCMU_PER1CLK,
|
||||
PRCMU_PER2CLK,
|
||||
PRCMU_PER3CLK,
|
||||
PRCMU_PER5CLK,
|
||||
PRCMU_PER6CLK,
|
||||
PRCMU_PER7CLK,
|
||||
PRCMU_LCDCLK,
|
||||
PRCMU_BMLCLK,
|
||||
PRCMU_HSITXCLK,
|
||||
PRCMU_HSIRXCLK,
|
||||
PRCMU_HDMICLK,
|
||||
PRCMU_APEATCLK,
|
||||
PRCMU_APETRACECLK,
|
||||
PRCMU_MCDECLK,
|
||||
PRCMU_IPI2CCLK,
|
||||
PRCMU_DSIALTCLK,
|
||||
PRCMU_DMACLK,
|
||||
PRCMU_B2R2CLK,
|
||||
PRCMU_TVCLK,
|
||||
PRCMU_SSPCLK,
|
||||
PRCMU_RNGCLK,
|
||||
PRCMU_UICCCLK,
|
||||
PRCMU_NUM_REG_CLOCKS,
|
||||
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
|
||||
PRCMU_TIMCLK,
|
||||
};
|
||||
|
||||
/*
|
||||
* Definitions for controlling ESRAM0 in deep sleep.
|
||||
*/
|
||||
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
|
||||
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
|
||||
|
||||
#ifdef CONFIG_MFD_DB8500_PRCMU
|
||||
void __init prcmu_early_init(void);
|
||||
int prcmu_set_display_clocks(void);
|
||||
int prcmu_disable_dsipll(void);
|
||||
int prcmu_enable_dsipll(void);
|
||||
#else
|
||||
static inline void __init prcmu_early_init(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MFD_DB8500_PRCMU
|
||||
|
||||
void db8500_prcmu_early_init(void);
|
||||
int prcmu_set_rc_a2p(enum romcode_write);
|
||||
enum romcode_read prcmu_get_rc_p2a(void);
|
||||
enum ap_pwrst prcmu_get_xp70_current_state(void);
|
||||
int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
|
||||
|
||||
void prcmu_enable_wakeups(u32 wakeups);
|
||||
static inline void prcmu_disable_wakeups(void)
|
||||
{
|
||||
prcmu_enable_wakeups(0);
|
||||
}
|
||||
|
||||
void prcmu_config_abb_event_readout(u32 abb_events);
|
||||
void prcmu_get_abb_event_buffer(void __iomem **buf);
|
||||
int prcmu_set_arm_opp(u8 opp);
|
||||
int prcmu_get_arm_opp(void);
|
||||
bool prcmu_has_arm_maxopp(void);
|
||||
bool prcmu_is_u8400(void);
|
||||
int prcmu_set_ape_opp(u8 opp);
|
||||
|
|
@ -710,19 +507,14 @@ int prcmu_request_ape_opp_100_voltage(bool enable);
|
|||
int prcmu_release_usb_wakeup_state(void);
|
||||
int prcmu_set_ddr_opp(u8 opp);
|
||||
int prcmu_get_ddr_opp(void);
|
||||
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
|
||||
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
|
||||
/* NOTE! Use regulator framework instead */
|
||||
int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
|
||||
int prcmu_set_epod(u16 epod_id, u8 epod_state);
|
||||
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
|
||||
struct prcmu_auto_pm_config *idle);
|
||||
bool prcmu_is_auto_pm_enabled(void);
|
||||
|
||||
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
|
||||
int prcmu_request_clock(u8 clock, bool enable);
|
||||
int prcmu_set_clock_divider(u8 clock, u8 divider);
|
||||
int prcmu_config_esram0_deep_sleep(u8 state);
|
||||
int prcmu_config_hotdog(u8 threshold);
|
||||
int prcmu_config_hotmon(u8 low, u8 high);
|
||||
int prcmu_start_temp_sense(u16 cycles32k);
|
||||
|
|
@ -732,14 +524,36 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
|
|||
|
||||
void prcmu_ac_wake_req(void);
|
||||
void prcmu_ac_sleep_req(void);
|
||||
void prcmu_system_reset(u16 reset_code);
|
||||
void prcmu_modem_reset(void);
|
||||
bool prcmu_is_ac_wake_requested(void);
|
||||
void prcmu_enable_spi2(void);
|
||||
void prcmu_disable_spi2(void);
|
||||
|
||||
int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
|
||||
int prcmu_enable_a9wdog(u8 id);
|
||||
int prcmu_disable_a9wdog(u8 id);
|
||||
int prcmu_kick_a9wdog(u8 id);
|
||||
int prcmu_load_a9wdog(u8 id, u32 val);
|
||||
|
||||
void db8500_prcmu_system_reset(u16 reset_code);
|
||||
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
|
||||
void db8500_prcmu_enable_wakeups(u32 wakeups);
|
||||
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
|
||||
int db8500_prcmu_request_clock(u8 clock, bool enable);
|
||||
int db8500_prcmu_set_display_clocks(void);
|
||||
int db8500_prcmu_disable_dsipll(void);
|
||||
int db8500_prcmu_enable_dsipll(void);
|
||||
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
|
||||
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
|
||||
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
|
||||
u16 db8500_prcmu_get_reset_code(void);
|
||||
bool db8500_prcmu_is_ac_wake_requested(void);
|
||||
int db8500_prcmu_set_arm_opp(u8 opp);
|
||||
int db8500_prcmu_get_arm_opp(void);
|
||||
|
||||
#else /* !CONFIG_MFD_DB8500_PRCMU */
|
||||
|
||||
static inline void db8500_prcmu_early_init(void) {}
|
||||
|
||||
static inline int prcmu_set_rc_a2p(enum romcode_write code)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -755,34 +569,12 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
|
|||
return AP_EXECUTE;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_enable_wakeups(u32 wakeups) {}
|
||||
|
||||
static inline void prcmu_disable_wakeups(void) {}
|
||||
|
||||
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
|
||||
|
||||
static inline int prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_get_arm_opp(void)
|
||||
{
|
||||
return ARM_100_OPP;
|
||||
}
|
||||
|
||||
static bool prcmu_has_arm_maxopp(void)
|
||||
static inline bool prcmu_has_arm_maxopp(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool prcmu_is_u8400(void)
|
||||
static inline bool prcmu_is_u8400(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
|
@ -817,13 +609,6 @@ static inline int prcmu_get_ddr_opp(void)
|
|||
return DDR_100_OPP;
|
||||
}
|
||||
|
||||
static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
|
||||
|
||||
static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -844,21 +629,11 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_hotdog(u8 threshold)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -893,32 +668,8 @@ static inline void prcmu_ac_wake_req(void) {}
|
|||
|
||||
static inline void prcmu_ac_sleep_req(void) {}
|
||||
|
||||
static inline void prcmu_system_reset(u16 reset_code) {}
|
||||
|
||||
static inline void prcmu_modem_reset(void) {}
|
||||
|
||||
static inline bool prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_UX500_SOC_DB5500
|
||||
static inline int prcmu_set_display_clocks(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int prcmu_enable_spi2(void)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -929,50 +680,95 @@ static inline int prcmu_disable_spi2(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
|
||||
|
||||
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
|
||||
|
||||
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_set_display_clocks(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_disable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_enable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
|
||||
|
||||
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
|
||||
|
||||
static inline u16 db8500_prcmu_get_reset_code(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_a9wdog(u8 id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_a9wdog(u8 id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_kick_a9wdog(u8 id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_load_a9wdog(u8 id, u32 val)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool db8500_prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_get_arm_opp(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_MFD_DB8500_PRCMU */
|
||||
|
||||
#ifdef CONFIG_UX500_PRCMU_QOS_POWER
|
||||
int prcmu_qos_requirement(int pm_qos_class);
|
||||
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
|
||||
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
|
||||
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
|
||||
int prcmu_qos_add_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier);
|
||||
int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier);
|
||||
#else
|
||||
static inline int prcmu_qos_requirement(int prcmu_qos_class)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
|
||||
char *name, s32 value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
|
||||
char *name, s32 new_value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __MFD_DB8500_PRCMU_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue