GitHub-Mirror/Star64_linux
2
0
Fork 0
mirror of https://github.com/Fishwaldo/Star64_linux.git synced 2025-03-16 12:14:06 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

riscv: Implement non-coherent DMA support via SiFive cache flushing

Browse source 
This variant is used on the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
This commit is contained in:
Emil Renner Berthing 2023-06-26 14:39:39 +08:00 • committed by Hal Feng
parent 4b7881a978
commit 7487d2ae15
2 changed files with 35 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
arch/riscv/Kconfig
View file

@ -267,8 +267,11 @@ config LOCKDEP_SUPPORT
def_bool y
config RISCV_DMA_NONCOHERENT
bool
bool "Support non-coherent DMA"
default SOC_STARFIVE
select ARCH_HAS_DMA_PREP_COHERENT
select ARCH_HAS_DMA_SET_UNCACHED
select ARCH_HAS_DMA_CLEAR_UNCACHED
select ARCH_HAS_SETUP_DMA_OPS
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE

31
arch/riscv/mm/dma-noncoherent.c
View file

@ -10,6 +10,7 @@
#include <linux/mm.h>
#include <asm/cacheflush.h>
#include <asm/dma-noncoherent.h>
#include <soc/sifive/sifive_ccache.h>
static bool noncoherent_supported __ro_after_init;
int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
@ -69,6 +70,11 @@ static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
{
if (sifive_ccache_handle_noncoherent()) {
sifive_ccache_flush_range(paddr, size);
return;
}
switch (dir) {
case DMA_TO_DEVICE:
arch_dma_cache_wback(paddr, size);
@ -98,6 +104,11 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
{
if (sifive_ccache_handle_noncoherent()) {
sifive_ccache_flush_range(paddr, size);
return;
}
switch (dir) {
case DMA_TO_DEVICE:
break;
@ -114,10 +125,30 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
}
}
void *arch_dma_set_uncached(void *addr, size_t size)
{
if (sifive_ccache_handle_noncoherent())
return sifive_ccache_set_uncached(addr, size);
return addr;
}
void arch_dma_clear_uncached(void *addr, size_t size)
{
if (sifive_ccache_handle_noncoherent())
sifive_ccache_clear_uncached(addr, size);
}
void arch_dma_prep_coherent(struct page *page, size_t size)
{
void *flush_addr = page_address(page);
if (sifive_ccache_handle_noncoherent()) {
memset(flush_addr, 0, size);
sifive_ccache_flush_range(__pa(flush_addr), size);
return;
}
#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
if (unlikely(noncoherent_cache_ops.wback_inv)) {
noncoherent_cache_ops.wback_inv(page_to_phys(page), size);