mirror of
https://github.com/Fishwaldo/Star64_linux.git
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Merge branch 'CR_2121_CAN_515_william.qiu' into 'jh7110-5.15.y-devel'
Cr 2121 can 515 william.qiu See merge request sdk/linux!477
This commit is contained in:
andy.hu
commit
75e57f02a6
9 changed files with 330 additions and 7 deletions
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@ -0,0 +1,77 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/starfive,jh7110-sdio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 SDIO Device Tree Bindings
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description: |
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Bindings for the JH7110 RISC-V SoC from StarFive Ltd.
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maintainers:
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- William Qiu <william,qiu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-sdio
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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-description: biu clock
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-description: ciu clock
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clock-names:
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minItems: 1
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items:
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-const: biu
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-const: ciu
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resets:
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maxItems: 1
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reset-names:
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maxItems: 1
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-const: reset
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interrupts:
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maxItems: 1
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fifo-depth:
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maxItems: 1
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data-addr:
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maxItem: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- interrupts
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- fifo-depth
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- data-addr
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examples:
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- |
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sdio0: sdio0@16010000 {
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compatible = "starfive,jh7110-sdio";
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reg = <0x0 0x16010000 0x0 0x10000>;
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clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
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<&clkgen JH7110_SDIO0_CLK_SDCARD>;
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clock-names = "biu","ciu";
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resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
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reset-names = "reset";
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interrupts = <74>;
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fifo-depth = <32>;
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fifo-watermark-aligned;
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data-addr = <0>;
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starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
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status = "disabled";
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};
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@ -20852,3 +20852,7 @@ M: Jianlong Huang <jianlong.huang@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
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STARFIVE JH7110 SDIO
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M: William Qiu <william.qiu@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/mmc/starfive,jh7110-sdio.yaml
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@ -27,13 +27,12 @@
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};
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&sdio0 {
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clock-frequency = <102400000>;
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max-frequency = <100000000>;
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card-detect-delay = <300>;
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bus-width = <8>;
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cap-mmc-highspeed;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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cap-mmc-hw-reset;
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post-power-on-delay-ms = <200>;
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@ -14,11 +14,17 @@
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/* default sd card */
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&sdio0 {
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clock-frequency = <102400000>;
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max-frequency = <200000000>;
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max-frequency = <100000000>;
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card-detect-delay = <300>;
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bus-width = <4>;
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no-sdio;
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no-mmc;
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broken-cd;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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cap-sd-highspeed;
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post-power-on-delay-ms = <200>;
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status = "okay";
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@ -842,7 +842,7 @@
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/* unremovable emmc as mmcblk0 */
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sdio0: sdio0@16010000 {
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compatible = "starfive,jh7110-sdio", "snps,dw-mshc";
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compatible = "starfive,jh7110-sdio";
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reg = <0x0 0x16010000 0x0 0x10000>;
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clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
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<&clkgen JH7110_SDIO0_CLK_SDCARD>;
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@ -853,11 +853,12 @@
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fifo-depth = <32>;
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fifo-watermark-aligned;
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data-addr = <0>;
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starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
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status = "disabled";
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};
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sdio1: sdio1@16020000 {
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compatible = "starfive,jh7110-sdio", "snps,dw-mshc";
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compatible = "starfive,jh7110-sdio";
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reg = <0x0 0x16020000 0x0 0x10000>;
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clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
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<&clkgen JH7110_SDIO1_CLK_SDCARD>;
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@ -232,6 +232,7 @@ CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MMC_SDHCI_OF_DWCMSHC=y
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CONFIG_MMC_SPI=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_STARFIVE=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_STARFIVE=y
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CONFIG_RTC_DRV_GOLDFISH=y
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@ -837,6 +837,15 @@ config MMC_DW_HI3798CV200
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on HiSilicon Hi3798CV200 SoC.
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config MMC_DW_STARFIVE
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tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
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depends on MMC_DW
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select MMC_DW_PLTFM
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help
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This selects support for StarFive JH7110 SoC specific extensions to the
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on Starfive JH7110 SoC.
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config MMC_DW_K3
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tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
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depends on MMC_DW
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@ -51,6 +51,7 @@ thunderx-mmc-objs := cavium.o cavium-thunderx.o
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obj-$(CONFIG_MMC_CAVIUM_THUNDERX) += thunderx-mmc.o
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obj-$(CONFIG_MMC_DW) += dw_mmc.o
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obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o
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obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
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obj-$(CONFIG_MMC_DW_BLUEFIELD) += dw_mmc-bluefield.o
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obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o
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obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
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225
drivers/mmc/host/dw_mmc-starfive.c
Normal file
225
drivers/mmc/host/dw_mmc-starfive.c
Normal file
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@ -0,0 +1,225 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2022 StarFive, Inc <clivia.cai@starfivetech.com>
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*
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
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* CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER
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* FOR THEM TO SAVE TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE
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* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
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* CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE
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* BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION
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* WITH THEIR PRODUCTS.
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*/
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define ALL_INT_CLR 0x1ffff
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#define MAX_DELAY_CHAIN 32
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struct starfive_priv {
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struct device *dev;
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struct regmap *reg_syscon;
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u32 syscon_offset;
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u32 syscon_shift;
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u32 syscon_mask;
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};
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static unsigned long dw_mci_starfive_caps[] = {
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23
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};
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static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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int ret;
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unsigned int clock;
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if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
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clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
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ret = clk_set_rate(host->ciu_clk, clock);
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if (ret)
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dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
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host->bus_hz = clk_get_rate(host->ciu_clk);
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} else {
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dev_dbg(host->dev, "Using the internal divider\n");
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}
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}
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static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
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u32 opcode)
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{
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static const int grade = MAX_DELAY_CHAIN;
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struct dw_mci *host = slot->host;
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struct starfive_priv *priv = host->priv;
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int raise_point = -1, fall_point = -1;
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int err, prev_err = -1;
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int found = 0;
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int i;
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u32 regval;
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for (i = 0; i < grade; i++) {
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regval = i << priv->syscon_shift;
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err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset, priv->syscon_mask, regval);
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if (err)
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return err;
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mci_writel(host, RINTSTS, ALL_INT_CLR);
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err = mmc_send_tuning(slot->mmc, opcode, NULL);
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if (!err)
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found = 1;
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if (i > 0) {
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if (err && !prev_err)
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fall_point = i - 1;
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if (!err && prev_err)
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raise_point = i;
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}
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if (raise_point != -1 && fall_point != -1)
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goto tuning_out;
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prev_err = err;
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err = 0;
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}
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tuning_out:
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if (found) {
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if (raise_point == -1)
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raise_point = 0;
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if (fall_point == -1)
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fall_point = grade - 1;
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if (fall_point < raise_point) {
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if ((raise_point + fall_point) >
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(grade - 1))
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i = fall_point / 2;
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else
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i = (raise_point + grade - 1) / 2;
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} else {
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i = (raise_point + fall_point) / 2;
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}
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regval = i << priv->syscon_shift;
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err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset, priv->syscon_mask, regval);
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if (err)
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return err;
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dev_dbg(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
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} else {
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dev_err(host->dev, "No valid delay chain! use default\n");
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err = -EINVAL;
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}
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mci_writel(host, RINTSTS, ALL_INT_CLR);
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return err;
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}
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static int dw_mci_starfive_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct dw_mci_slot *slot = mmc_priv(mmc);
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struct dw_mci *host = slot->host;
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u32 ret;
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
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ret = gpio_direction_output(25, 0);
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else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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ret = gpio_direction_output(25, 1);
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if (ret)
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return ret;
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if (!IS_ERR(mmc->supply.vqmmc)) {
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ret = mmc_regulator_set_vqmmc(mmc, ios);
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if (ret < 0) {
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dev_err(host->dev, "Regulator set error %d\n", ret);
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return ret;
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}
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}
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/* We should delay 20ms wait for timing setting finished. */
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mdelay(20);
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return 0;
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}
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static int dw_mci_starfive_parse_dt(struct dw_mci *host)
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{
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struct of_phandle_args args;
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struct starfive_priv *priv;
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int ret;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
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"starfive,sys-syscon", 3, 0, &args);
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if (ret) {
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dev_err(host->dev, "Failed to parse starfive,sys-syscon\n");
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return -EINVAL;
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}
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priv->reg_syscon = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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if (IS_ERR(priv->reg_syscon))
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return PTR_ERR(priv->reg_syscon);
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priv->syscon_offset = args.args[0];
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priv->syscon_shift = args.args[1];
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priv->syscon_mask = args.args[2];
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host->priv = priv;
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return 0;
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}
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static const struct dw_mci_drv_data starfive_data = {
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.caps = dw_mci_starfive_caps,
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.num_caps = ARRAY_SIZE(dw_mci_starfive_caps),
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.set_ios = dw_mci_starfive_set_ios,
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.parse_dt = dw_mci_starfive_parse_dt,
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.execute_tuning = dw_mci_starfive_execute_tuning,
|
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.switch_voltage = dw_mci_starfive_switch_voltage,
|
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};
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static int dw_mci_starfive_probe(struct platform_device *pdev)
|
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{
|
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return dw_mci_pltfm_register(pdev, &starfive_data);
|
||||
}
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||||
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||||
static int dw_mci_starfive_remove(struct platform_device *pdev)
|
||||
{
|
||||
return dw_mci_pltfm_remove(pdev);
|
||||
}
|
||||
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||||
static const struct of_device_id dw_mci_starfive_match[] = {
|
||||
{ .compatible = "starfive,jh7110-sdio", },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
|
||||
static struct platform_driver dw_mci_starfive_driver = {
|
||||
.probe = dw_mci_starfive_probe,
|
||||
.remove = dw_mci_starfive_remove,
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.driver = {
|
||||
.name = "dwmmc_starfive",
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||||
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
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.of_match_table = dw_mci_starfive_match,
|
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},
|
||||
};
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||||
module_platform_driver(dw_mci_starfive_driver);
|
||||
|
||||
MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:dwmmc_starfive");
|
||||
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