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riscv: Implement non-coherent DMA support via SiFive cache flushing
This variant is used on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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parent
4dee2cd243
commit
7735322fcf
2 changed files with 39 additions and 4 deletions
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@ -233,12 +233,14 @@ config LOCKDEP_SUPPORT
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def_bool y
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config RISCV_DMA_NONCOHERENT
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bool
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bool "Support non-coherent DMA"
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default SOC_STARFIVE
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select ARCH_HAS_DMA_PREP_COHERENT
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select ARCH_HAS_DMA_SET_UNCACHED
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select ARCH_HAS_DMA_CLEAR_UNCACHED
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SETUP_DMA_OPS
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select DMA_DIRECT_REMAP
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config AS_HAS_INSN
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def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
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@ -9,14 +9,21 @@
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#include <linux/dma-map-ops.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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#include <soc/sifive/sifive_ccache.h>
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static bool noncoherent_supported;
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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void *vaddr;
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if (sifive_ccache_handle_noncoherent()) {
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sifive_ccache_flush_range(paddr, size);
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return;
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}
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vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_TO_DEVICE:
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ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
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@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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void *vaddr;
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if (sifive_ccache_handle_noncoherent()) {
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sifive_ccache_flush_range(paddr, size);
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return;
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}
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vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_TO_DEVICE:
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break;
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@ -49,10 +62,30 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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}
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}
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void *arch_dma_set_uncached(void *addr, size_t size)
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{
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if (sifive_ccache_handle_noncoherent())
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return sifive_ccache_set_uncached(addr, size);
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return addr;
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}
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void arch_dma_clear_uncached(void *addr, size_t size)
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{
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if (sifive_ccache_handle_noncoherent())
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sifive_ccache_clear_uncached(addr, size);
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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void *flush_addr = page_address(page);
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if (sifive_ccache_handle_noncoherent()) {
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memset(flush_addr, 0, size);
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sifive_ccache_flush_range(__pa(flush_addr), size);
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return;
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}
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ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
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}
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