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spi/pl022: add support for the PL023 derivate
This adds support for a further ST variant of the PL022 called PL023. Some differences in the control registers due to being stripped down to SPI mode only, and a new clock feedback sample delay config setting is available. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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2 changed files with 104 additions and 18 deletions
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@ -182,8 +182,8 @@ enum ssp_microwire_wait_state {
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};
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/**
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* enum Microwire - whether Full/Half Duplex, only available
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* in the ST Micro variant.
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* enum ssp_duplex - whether Full/Half Duplex on microwire, only
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* available in the ST Micro variant.
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* @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
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* SSPRXD not used
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* @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
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@ -194,6 +194,31 @@ enum ssp_duplex {
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SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
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};
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/**
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* enum ssp_clkdelay - an optional clock delay on the feedback clock
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* only available in the ST Micro PL023 variant.
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* @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
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* slave is sampled directly
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* @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
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* a delay of T-dt
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* @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
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* @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
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* @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
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* @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
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* @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
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* @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
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*/
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enum ssp_clkdelay {
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SSP_FEEDBACK_CLK_DELAY_NONE,
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SSP_FEEDBACK_CLK_DELAY_1T,
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SSP_FEEDBACK_CLK_DELAY_2T,
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SSP_FEEDBACK_CLK_DELAY_3T,
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SSP_FEEDBACK_CLK_DELAY_4T,
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SSP_FEEDBACK_CLK_DELAY_5T,
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SSP_FEEDBACK_CLK_DELAY_6T,
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SSP_FEEDBACK_CLK_DELAY_7T
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};
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/**
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* CHIP select/deselect commands
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*/
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@ -237,6 +262,8 @@ struct pl022_ssp_controller {
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* @ctrl_len: Microwire interface: Control length
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* @wait_state: Microwire interface: Wait state
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* @duplex: Microwire interface: Full/Half duplex
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* @clkdelay: on the PL023 variant, the delay in feeback clock cycles
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* before sampling the incoming line
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* @cs_control: function pointer to board-specific function to
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* assert/deassert I/O port to control HW generation of devices chip-select.
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* @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph)
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@ -260,6 +287,7 @@ struct pl022_config_chip {
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enum ssp_microwire_ctrl_len ctrl_len;
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enum ssp_microwire_wait_state wait_state;
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enum ssp_duplex duplex;
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enum ssp_clkdelay clkdelay;
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void (*cs_control) (u32 control);
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};
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