mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-06-29 10:01:25 +00:00
Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (82 commits) mtd: fix build error in m25p80.c mtd: Remove redundant mutex from mtd_blkdevs.c MTD: Fix wrong check register_blkdev return value Revert "mtd: cleanup Kconfig dependencies" mtd: cfi_cmdset_0002: make sector erase command variable mtd: cfi_cmdset_0002: add CFI detection for SST 38VF640x chips mtd: cfi_util: add support for switching SST 39VF640xB chips into QRY mode mtd: cfi_cmdset_0001: use defined value of P_ID_INTEL_PERFORMANCE instead of hardcoded one block2mtd: dubious assignment P4080/mtd: Fix the freescale lbc issue with 36bit mode P4080/eLBC: Make Freescale elbc interrupt common to elbc devices mtd: phram: use KBUILD_MODNAME mtd: OneNAND: S5PC110: Fix double call suspend & resume function mtd: nand: fix MTD_MODE_RAW writes jffs2: use kmemdup mtd: sm_ftl: cosmetic, use bool when possible mtd: r852: remove useless pci powerup/down from suspend/resume routines mtd: blktrans: fix a race vs kthread_stop mtd: blktrans: kill BKL mtd: allow to unload the mtdtrans module if its block devices aren't open ... Fix up trivial whitespace-introduced conflict in drivers/mtd/mtdchar.c
This commit is contained in:
Linus Torvalds
commit
79346507ad
71 changed files with 3404 additions and 1151 deletions
|
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@ -84,7 +84,7 @@ struct nand_bbt_descr {
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#define NAND_BBT_PERCHIP 0x00000080
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/* bbt has a version counter at offset veroffs */
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#define NAND_BBT_VERSION 0x00000100
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/* Create a bbt if none axists */
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/* Create a bbt if none exists */
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#define NAND_BBT_CREATE 0x00000200
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/* Search good / bad pattern through all pages of a block */
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#define NAND_BBT_SCANALLPAGES 0x00000400
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@ -102,6 +102,8 @@ struct nand_bbt_descr {
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#define NAND_BBT_SCANBYTE1AND6 0x00100000
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/* The nand_bbt_descr was created dynamicaly and must be freed */
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#define NAND_BBT_DYNAMICSTRUCT 0x00200000
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/* The bad block table does not OOB for marker */
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#define NAND_BBT_NO_OOB 0x00400000
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/* The maximum number of blocks to scan for a bbt */
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#define NAND_BBT_SCAN_MAXBLOCKS 4
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@ -289,6 +289,7 @@ struct cfi_private {
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must be of the same type. */
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int mfr, id;
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int numchips;
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map_word sector_erase_cmd;
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unsigned long chipshift; /* Because they're of the same type */
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const char *im_name; /* inter_module name for cmdset_setup */
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struct flchip chips[0]; /* per-chip data structure for each chip */
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181
include/linux/mtd/fsmc.h
Normal file
181
include/linux/mtd/fsmc.h
Normal file
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@ -0,0 +1,181 @@
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/*
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* incude/mtd/fsmc.h
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*
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* ST Microelectronics
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* Flexible Static Memory Controller (FSMC)
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* platform data interface and header file
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*
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* Copyright © 2010 ST Microelectronics
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* Vipin Kumar <vipin.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MTD_FSMC_H
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#define __MTD_FSMC_H
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/types.h>
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#include <linux/mtd/partitions.h>
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#include <asm/param.h>
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#define FSMC_NAND_BW8 1
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#define FSMC_NAND_BW16 2
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/*
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* The placement of the Command Latch Enable (CLE) and
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* Address Latch Enable (ALE) is twised around in the
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* SPEAR310 implementation.
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*/
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#if defined(CONFIG_MACH_SPEAR310)
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#define PLAT_NAND_CLE (1 << 17)
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#define PLAT_NAND_ALE (1 << 16)
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#else
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#define PLAT_NAND_CLE (1 << 16)
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#define PLAT_NAND_ALE (1 << 17)
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#endif
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#define FSMC_MAX_NOR_BANKS 4
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#define FSMC_MAX_NAND_BANKS 4
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#define FSMC_FLASH_WIDTH8 1
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#define FSMC_FLASH_WIDTH16 2
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struct fsmc_nor_bank_regs {
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uint32_t ctrl;
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uint32_t ctrl_tim;
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};
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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/* ctrl_tim register definitions */
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struct fsms_nand_bank_regs {
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uint32_t pc;
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uint32_t sts;
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uint32_t comm;
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uint32_t attrib;
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uint32_t ioata;
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uint32_t ecc1;
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uint32_t ecc2;
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uint32_t ecc3;
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};
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#define FSMC_NOR_REG_SIZE 0x40
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struct fsmc_regs {
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struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
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uint8_t reserved_1[0x40 - 0x20];
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struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
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uint8_t reserved_2[0xfe0 - 0xc0];
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uint32_t peripid0; /* 0xfe0 */
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uint32_t peripid1; /* 0xfe4 */
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uint32_t peripid2; /* 0xfe8 */
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uint32_t peripid3; /* 0xfec */
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uint32_t pcellid0; /* 0xff0 */
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uint32_t pcellid1; /* 0xff4 */
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uint32_t pcellid2; /* 0xff8 */
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uint32_t pcellid3; /* 0xffc */
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};
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1 << 9)
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#define FSMC_TAR_1 (1 << 13)
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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/* comm register definitions */
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#define FSMC_TSET_0 (0 << 0)
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#define FSMC_TWAIT_6 (6 << 8)
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#define FSMC_THOLD_4 (4 << 16)
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#define FSMC_THIZ_1 (1 << 24)
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/* peripid2 register definitions */
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#define FSMC_REVISION_MSK (0xf)
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#define FSMC_REVISION_SHFT (0x4)
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#define FSMC_VER1 1
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#define FSMC_VER2 2
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#define FSMC_VER3 3
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#define FSMC_VER4 4
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#define FSMC_VER5 5
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#define FSMC_VER6 6
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#define FSMC_VER7 7
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#define FSMC_VER8 8
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static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
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{
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return (readl(®s->peripid2) >> FSMC_REVISION_SHFT) &
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FSMC_REVISION_MSK;
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}
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/*
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* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
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* and it has to be read consecutively and immediately after the 512
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* byte data block for hardware to generate the error bit offsets
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* Managing the ecc bytes in the following way is easier. This way is
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* similar to oobfree structure maintained already in u-boot nand driver
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*/
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#define MAX_ECCPLACE_ENTRIES 32
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struct fsmc_nand_eccplace {
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uint8_t offset;
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uint8_t length;
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};
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struct fsmc_eccplace {
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struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
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};
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/**
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* fsmc_nand_platform_data - platform specific NAND controller config
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* @partitions: partition table for the platform, use a default fallback
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* if this is NULL
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* @nr_partitions: the number of partitions in the previous entry
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* @options: different options for the driver
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* @width: bus width
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* @bank: default bank
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* @select_bank: callback to select a certain bank, this is
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* platform-specific. If the controller only supports one bank
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* this may be set to NULL
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*/
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struct fsmc_nand_platform_data {
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struct mtd_partition *partitions;
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unsigned int nr_partitions;
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unsigned int options;
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unsigned int width;
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unsigned int bank;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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};
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extern int __init fsmc_nor_init(struct platform_device *pdev,
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unsigned long base, uint32_t bank, uint32_t width);
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extern void __init fsmc_init_board_info(struct platform_device *pdev,
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struct mtd_partition *partitions, unsigned int nr_partitions,
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unsigned int width);
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#endif /* __MTD_FSMC_H */
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@ -37,14 +37,14 @@ struct INFTLrecord {
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__u16 firstEUN;
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__u16 lastEUN;
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__u16 numfreeEUNs;
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__u16 LastFreeEUN; /* To speed up finding a free EUN */
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__u16 LastFreeEUN; /* To speed up finding a free EUN */
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int head,sect,cyl;
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__u16 *PUtable; /* Physical Unit Table */
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__u16 *VUtable; /* Virtual Unit Table */
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unsigned int nb_blocks; /* number of physical blocks */
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unsigned int nb_boot_blocks; /* number of blocks used by the bios */
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struct erase_info instr;
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struct nand_ecclayout oobinfo;
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__u16 *PUtable; /* Physical Unit Table */
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__u16 *VUtable; /* Virtual Unit Table */
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unsigned int nb_blocks; /* number of physical blocks */
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unsigned int nb_boot_blocks; /* number of blocks used by the bios */
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struct erase_info instr;
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struct nand_ecclayout oobinfo;
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};
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int INFTL_mount(struct INFTLrecord *s);
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|
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@ -110,6 +110,21 @@ struct mtd_oob_ops {
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uint8_t *oobbuf;
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};
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#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
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#define MTD_MAX_ECCPOS_ENTRIES_LARGE 448
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/*
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* Internal ECC layout control structure. For historical reasons, there is a
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* similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained
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* for export to user-space via the ECCGETLAYOUT ioctl.
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* nand_ecclayout should be expandable in the future simply by the above macros.
|
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*/
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struct nand_ecclayout {
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__u32 eccbytes;
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__u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
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__u32 oobavail;
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struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
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};
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struct mtd_info {
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u_char type;
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uint32_t flags;
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|
|
|
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|
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@ -27,15 +27,17 @@
|
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struct mtd_info;
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struct nand_flash_dev;
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/* Scan and identify a NAND device */
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extern int nand_scan (struct mtd_info *mtd, int max_chips);
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/* Separate phases of nand_scan(), allowing board driver to intervene
|
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* and override command or ECC setup according to flash type */
|
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extern int nand_scan(struct mtd_info *mtd, int max_chips);
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/*
|
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* Separate phases of nand_scan(), allowing board driver to intervene
|
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* and override command or ECC setup according to flash type.
|
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*/
|
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extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
|
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struct nand_flash_dev *table);
|
||||
extern int nand_scan_tail(struct mtd_info *mtd);
|
||||
|
||||
/* Free resources held by the NAND device */
|
||||
extern void nand_release (struct mtd_info *mtd);
|
||||
extern void nand_release(struct mtd_info *mtd);
|
||||
|
||||
/* Internal helper for board drivers which need to override command function */
|
||||
extern void nand_wait_ready(struct mtd_info *mtd);
|
||||
|
|
@ -49,12 +51,13 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
|
|||
/* The maximum number of NAND chips in an array */
|
||||
#define NAND_MAX_CHIPS 8
|
||||
|
||||
/* This constant declares the max. oobsize / page, which
|
||||
/*
|
||||
* This constant declares the max. oobsize / page, which
|
||||
* is supported now. If you add a chip with bigger oobsize/page
|
||||
* adjust this accordingly.
|
||||
*/
|
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#define NAND_MAX_OOBSIZE 256
|
||||
#define NAND_MAX_PAGESIZE 4096
|
||||
#define NAND_MAX_OOBSIZE 576
|
||||
#define NAND_MAX_PAGESIZE 8192
|
||||
|
||||
/*
|
||||
* Constants for hardware specific CLE/ALE/NCE function
|
||||
|
|
@ -88,6 +91,7 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
|
|||
#define NAND_CMD_RNDIN 0x85
|
||||
#define NAND_CMD_READID 0x90
|
||||
#define NAND_CMD_ERASE2 0xd0
|
||||
#define NAND_CMD_PARAM 0xec
|
||||
#define NAND_CMD_RESET 0xff
|
||||
|
||||
#define NAND_CMD_LOCK 0x2a
|
||||
|
|
@ -152,9 +156,10 @@ typedef enum {
|
|||
#define NAND_GET_DEVICE 0x80
|
||||
|
||||
|
||||
/* Option constants for bizarre disfunctionality and real
|
||||
* features
|
||||
*/
|
||||
/*
|
||||
* Option constants for bizarre disfunctionality and real
|
||||
* features.
|
||||
*/
|
||||
/* Chip can not auto increment pages */
|
||||
#define NAND_NO_AUTOINCR 0x00000001
|
||||
/* Buswitdh is 16 bit */
|
||||
|
|
@ -165,19 +170,27 @@ typedef enum {
|
|||
#define NAND_CACHEPRG 0x00000008
|
||||
/* Chip has copy back function */
|
||||
#define NAND_COPYBACK 0x00000010
|
||||
/* AND Chip which has 4 banks and a confusing page / block
|
||||
* assignment. See Renesas datasheet for further information */
|
||||
/*
|
||||
* AND Chip which has 4 banks and a confusing page / block
|
||||
* assignment. See Renesas datasheet for further information.
|
||||
*/
|
||||
#define NAND_IS_AND 0x00000020
|
||||
/* Chip has a array of 4 pages which can be read without
|
||||
* additional ready /busy waits */
|
||||
/*
|
||||
* Chip has a array of 4 pages which can be read without
|
||||
* additional ready /busy waits.
|
||||
*/
|
||||
#define NAND_4PAGE_ARRAY 0x00000040
|
||||
/* Chip requires that BBT is periodically rewritten to prevent
|
||||
/*
|
||||
* Chip requires that BBT is periodically rewritten to prevent
|
||||
* bits from adjacent blocks from 'leaking' in altering data.
|
||||
* This happens with the Renesas AG-AND chips, possibly others. */
|
||||
* This happens with the Renesas AG-AND chips, possibly others.
|
||||
*/
|
||||
#define BBT_AUTO_REFRESH 0x00000080
|
||||
/* Chip does not require ready check on read. True
|
||||
/*
|
||||
* Chip does not require ready check on read. True
|
||||
* for all large page devices, as they do not support
|
||||
* autoincrement.*/
|
||||
* autoincrement.
|
||||
*/
|
||||
#define NAND_NO_READRDY 0x00000100
|
||||
/* Chip does not allow subpage writes */
|
||||
#define NAND_NO_SUBPAGE_WRITE 0x00000200
|
||||
|
|
@ -205,16 +218,27 @@ typedef enum {
|
|||
#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
|
||||
|
||||
/* Non chip related options */
|
||||
/* Use a flash based bad block table. This option is passed to the
|
||||
* default bad block table function. */
|
||||
/*
|
||||
* Use a flash based bad block table. OOB identifier is saved in OOB area.
|
||||
* This option is passed to the default bad block table function.
|
||||
*/
|
||||
#define NAND_USE_FLASH_BBT 0x00010000
|
||||
/* This option skips the bbt scan during initialization. */
|
||||
#define NAND_SKIP_BBTSCAN 0x00020000
|
||||
/* This option is defined if the board driver allocates its own buffers
|
||||
(e.g. because it needs them DMA-coherent */
|
||||
/*
|
||||
* This option is defined if the board driver allocates its own buffers
|
||||
* (e.g. because it needs them DMA-coherent).
|
||||
*/
|
||||
#define NAND_OWN_BUFFERS 0x00040000
|
||||
/* Chip may not exist, so silence any errors in scan */
|
||||
#define NAND_SCAN_SILENT_NODEV 0x00080000
|
||||
/*
|
||||
* If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
|
||||
* the OOB area.
|
||||
*/
|
||||
#define NAND_USE_FLASH_BBT_NO_OOB 0x00100000
|
||||
/* Create an empty BBT with no vendor information if the BBT is available */
|
||||
#define NAND_CREATE_EMPTY_BBT 0x00200000
|
||||
|
||||
/* Options set by nand scan */
|
||||
/* Nand scan has allocated controller struct */
|
||||
|
|
@ -227,15 +251,80 @@ typedef enum {
|
|||
/* Keep gcc happy */
|
||||
struct nand_chip;
|
||||
|
||||
struct nand_onfi_params {
|
||||
/* rev info and features block */
|
||||
/* 'O' 'N' 'F' 'I' */
|
||||
u8 sig[4];
|
||||
__le16 revision;
|
||||
__le16 features;
|
||||
__le16 opt_cmd;
|
||||
u8 reserved[22];
|
||||
|
||||
/* manufacturer information block */
|
||||
char manufacturer[12];
|
||||
char model[20];
|
||||
u8 jedec_id;
|
||||
__le16 date_code;
|
||||
u8 reserved2[13];
|
||||
|
||||
/* memory organization block */
|
||||
__le32 byte_per_page;
|
||||
__le16 spare_bytes_per_page;
|
||||
__le32 data_bytes_per_ppage;
|
||||
__le16 spare_bytes_per_ppage;
|
||||
__le32 pages_per_block;
|
||||
__le32 blocks_per_lun;
|
||||
u8 lun_count;
|
||||
u8 addr_cycles;
|
||||
u8 bits_per_cell;
|
||||
__le16 bb_per_lun;
|
||||
__le16 block_endurance;
|
||||
u8 guaranteed_good_blocks;
|
||||
__le16 guaranteed_block_endurance;
|
||||
u8 programs_per_page;
|
||||
u8 ppage_attr;
|
||||
u8 ecc_bits;
|
||||
u8 interleaved_bits;
|
||||
u8 interleaved_ops;
|
||||
u8 reserved3[13];
|
||||
|
||||
/* electrical parameter block */
|
||||
u8 io_pin_capacitance_max;
|
||||
__le16 async_timing_mode;
|
||||
__le16 program_cache_timing_mode;
|
||||
__le16 t_prog;
|
||||
__le16 t_bers;
|
||||
__le16 t_r;
|
||||
__le16 t_ccs;
|
||||
__le16 src_sync_timing_mode;
|
||||
__le16 src_ssync_features;
|
||||
__le16 clk_pin_capacitance_typ;
|
||||
__le16 io_pin_capacitance_typ;
|
||||
__le16 input_pin_capacitance_typ;
|
||||
u8 input_pin_capacitance_max;
|
||||
u8 driver_strenght_support;
|
||||
__le16 t_int_r;
|
||||
__le16 t_ald;
|
||||
u8 reserved4[7];
|
||||
|
||||
/* vendor */
|
||||
u8 reserved5[90];
|
||||
|
||||
__le16 crc;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define ONFI_CRC_BASE 0x4F4E
|
||||
|
||||
/**
|
||||
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
|
||||
* @lock: protection lock
|
||||
* @active: the mtd device which holds the controller currently
|
||||
* @wq: wait queue to sleep on if a NAND operation is in progress
|
||||
* used instead of the per chip wait queue when a hw controller is available
|
||||
* @wq: wait queue to sleep on if a NAND operation is in
|
||||
* progress used instead of the per chip wait queue
|
||||
* when a hw controller is available.
|
||||
*/
|
||||
struct nand_hw_control {
|
||||
spinlock_t lock;
|
||||
spinlock_t lock;
|
||||
struct nand_chip *active;
|
||||
wait_queue_head_t wq;
|
||||
};
|
||||
|
|
@ -256,51 +345,42 @@ struct nand_hw_control {
|
|||
* @correct: function for ecc correction, matching to ecc generator (sw/hw)
|
||||
* @read_page_raw: function to read a raw page without ECC
|
||||
* @write_page_raw: function to write a raw page without ECC
|
||||
* @read_page: function to read a page according to the ecc generator requirements
|
||||
* @read_page: function to read a page according to the ecc generator
|
||||
* requirements.
|
||||
* @read_subpage: function to read parts of the page covered by ECC.
|
||||
* @write_page: function to write a page according to the ecc generator requirements
|
||||
* @write_page: function to write a page according to the ecc generator
|
||||
* requirements.
|
||||
* @read_oob: function to read chip OOB data
|
||||
* @write_oob: function to write chip OOB data
|
||||
*/
|
||||
struct nand_ecc_ctrl {
|
||||
nand_ecc_modes_t mode;
|
||||
int steps;
|
||||
int size;
|
||||
int bytes;
|
||||
int total;
|
||||
int prepad;
|
||||
int postpad;
|
||||
nand_ecc_modes_t mode;
|
||||
int steps;
|
||||
int size;
|
||||
int bytes;
|
||||
int total;
|
||||
int prepad;
|
||||
int postpad;
|
||||
struct nand_ecclayout *layout;
|
||||
void (*hwctl)(struct mtd_info *mtd, int mode);
|
||||
int (*calculate)(struct mtd_info *mtd,
|
||||
const uint8_t *dat,
|
||||
uint8_t *ecc_code);
|
||||
int (*correct)(struct mtd_info *mtd, uint8_t *dat,
|
||||
uint8_t *read_ecc,
|
||||
uint8_t *calc_ecc);
|
||||
int (*read_page_raw)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf, int page);
|
||||
void (*write_page_raw)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_page)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf, int page);
|
||||
int (*read_subpage)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint32_t offs, uint32_t len,
|
||||
uint8_t *buf);
|
||||
void (*write_page)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_oob)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
int page,
|
||||
int sndcmd);
|
||||
int (*write_oob)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
int page);
|
||||
void (*hwctl)(struct mtd_info *mtd, int mode);
|
||||
int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
|
||||
uint8_t *ecc_code);
|
||||
int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
|
||||
uint8_t *calc_ecc);
|
||||
int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf, int page);
|
||||
void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf, int page);
|
||||
int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint32_t offs, uint32_t len, uint8_t *buf);
|
||||
void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
|
||||
int sndcmd);
|
||||
int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int page);
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -320,102 +400,132 @@ struct nand_buffers {
|
|||
|
||||
/**
|
||||
* struct nand_chip - NAND Private Flash Chip Data
|
||||
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
|
||||
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
|
||||
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
|
||||
* flash device
|
||||
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
|
||||
* flash device.
|
||||
* @read_byte: [REPLACEABLE] read one byte from the chip
|
||||
* @read_word: [REPLACEABLE] read one word from the chip
|
||||
* @write_buf: [REPLACEABLE] write data from the buffer to the chip
|
||||
* @read_buf: [REPLACEABLE] read data from the chip into the buffer
|
||||
* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
|
||||
* @verify_buf: [REPLACEABLE] verify buffer contents against the chip
|
||||
* data.
|
||||
* @select_chip: [REPLACEABLE] select chip nr
|
||||
* @block_bad: [REPLACEABLE] check, if the block is bad
|
||||
* @block_markbad: [REPLACEABLE] mark the block bad
|
||||
* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
|
||||
* ALE/CLE/nCE. Also used to write command and address
|
||||
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
|
||||
* If set to NULL no access to ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register
|
||||
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
|
||||
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
|
||||
* @init_size: [BOARDSPECIFIC] hardwarespecific funtion for setting
|
||||
* mtd->oobsize, mtd->writesize and so on.
|
||||
* @id_data contains the 8 bytes values of NAND_CMD_READID.
|
||||
* Return with the bus width.
|
||||
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
|
||||
* device ready/busy line. If set to NULL no access to
|
||||
* ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register.
|
||||
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
|
||||
* commands to the chip.
|
||||
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
|
||||
* ready.
|
||||
* @ecc: [BOARDSPECIFIC] ecc control ctructure
|
||||
* @buffers: buffer structure for read/write
|
||||
* @hwcontrol: platform-specific hardware control structure
|
||||
* @ops: oob operation operands
|
||||
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
|
||||
* @erase_cmd: [INTERN] erase command write function, selectable due
|
||||
* to AND support.
|
||||
* @scan_bbt: [REPLACEABLE] function to scan bad block table
|
||||
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
|
||||
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering
|
||||
* data from array to read regs (tR).
|
||||
* @state: [INTERN] the current state of the NAND device
|
||||
* @oob_poi: poison value buffer
|
||||
* @page_shift: [INTERN] number of address bits in a page (column address bits)
|
||||
* @page_shift: [INTERN] number of address bits in a page (column
|
||||
* address bits).
|
||||
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
|
||||
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
||||
* @chip_shift: [INTERN] number of address bits in one chip
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
|
||||
* special functionality. See the defines for further explanation
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob area
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly
|
||||
* be set to inform nand_scan about special functionality.
|
||||
* See the defines for further explanation.
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob
|
||||
* area.
|
||||
* @cellinfo: [INTERN] MLC/multichip data from chip ident
|
||||
* @numchips: [INTERN] number of physical chips
|
||||
* @chipsize: [INTERN] the size of one chip for multichip arrays
|
||||
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
|
||||
* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
|
||||
* @pagebuf: [INTERN] holds the pagenumber which is currently in
|
||||
* data_buf.
|
||||
* @subpagesize: [INTERN] holds the subpagesize
|
||||
* @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
|
||||
* non 0 if ONFI supported.
|
||||
* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
|
||||
* supported, 0 otherwise.
|
||||
* @ecclayout: [REPLACEABLE] the default ecc placement scheme
|
||||
* @bbt: [INTERN] bad block table pointer
|
||||
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
|
||||
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
|
||||
* lookup.
|
||||
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
|
||||
* @controller: [REPLACEABLE] a pointer to a hardware controller structure
|
||||
* which is shared among multiple independend devices
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
|
||||
* bad block scan.
|
||||
* @controller: [REPLACEABLE] a pointer to a hardware controller
|
||||
* structure which is shared among multiple independend
|
||||
* devices.
|
||||
* @priv: [OPTIONAL] pointer to private chip date
|
||||
* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
|
||||
* (determine if errors are correctable)
|
||||
* @errstat: [OPTIONAL] hardware specific function to perform
|
||||
* additional error status checks (determine if errors are
|
||||
* correctable).
|
||||
* @write_page: [REPLACEABLE] High-level page write function
|
||||
*/
|
||||
|
||||
struct nand_chip {
|
||||
void __iomem *IO_ADDR_R;
|
||||
void __iomem *IO_ADDR_W;
|
||||
void __iomem *IO_ADDR_R;
|
||||
void __iomem *IO_ADDR_W;
|
||||
|
||||
uint8_t (*read_byte)(struct mtd_info *mtd);
|
||||
u16 (*read_word)(struct mtd_info *mtd);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
||||
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
|
||||
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw);
|
||||
uint8_t (*read_byte)(struct mtd_info *mtd);
|
||||
u16 (*read_word)(struct mtd_info *mtd);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
||||
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
||||
int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
|
||||
u8 *id_data);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
|
||||
int page_addr);
|
||||
int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
|
||||
int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw);
|
||||
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int numchips;
|
||||
uint64_t chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
int badblockbits;
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int numchips;
|
||||
uint64_t chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
int badblockbits;
|
||||
|
||||
flstate_t state;
|
||||
int onfi_version;
|
||||
struct nand_onfi_params onfi_params;
|
||||
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
flstate_t state;
|
||||
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
|
||||
struct nand_ecc_ctrl ecc;
|
||||
struct nand_buffers *buffers;
|
||||
|
|
@ -423,13 +533,13 @@ struct nand_chip {
|
|||
|
||||
struct mtd_oob_ops ops;
|
||||
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
|
||||
void *priv;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -473,7 +583,7 @@ struct nand_flash_dev {
|
|||
*/
|
||||
struct nand_manufacturers {
|
||||
int id;
|
||||
char * name;
|
||||
char *name;
|
||||
};
|
||||
|
||||
extern struct nand_flash_dev nand_flash_ids[];
|
||||
|
|
@ -486,7 +596,7 @@ extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
|
|||
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
||||
int allowbbt);
|
||||
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
size_t * retlen, uint8_t * buf);
|
||||
size_t *retlen, uint8_t *buf);
|
||||
|
||||
/**
|
||||
* struct platform_nand_chip - chip level device structure
|
||||
|
|
@ -502,17 +612,16 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|||
* @priv: hardware controller specific settings
|
||||
*/
|
||||
struct platform_nand_chip {
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
const char **part_probe_types;
|
||||
void (*set_parts)(uint64_t size,
|
||||
struct platform_nand_chip *chip);
|
||||
void *priv;
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
const char **part_probe_types;
|
||||
void (*set_parts)(uint64_t size, struct platform_nand_chip *chip);
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/* Keep gcc happy */
|
||||
|
|
@ -534,18 +643,15 @@ struct platform_device;
|
|||
* All fields are optional and depend on the hardware driver requirements
|
||||
*/
|
||||
struct platform_nand_ctrl {
|
||||
int (*probe)(struct platform_device *pdev);
|
||||
void (*remove)(struct platform_device *pdev);
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
void (*write_buf)(struct mtd_info *mtd,
|
||||
const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd,
|
||||
uint8_t *buf, int len);
|
||||
void *priv;
|
||||
int (*probe)(struct platform_device *pdev);
|
||||
void (*remove)(struct platform_device *pdev);
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -554,8 +660,8 @@ struct platform_nand_ctrl {
|
|||
* @ctrl: controller level device structure
|
||||
*/
|
||||
struct platform_nand_data {
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
};
|
||||
|
||||
/* Some helpers to access the data structures */
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ struct mtd_partition {
|
|||
uint64_t size; /* partition size */
|
||||
uint64_t offset; /* offset within the master MTD space */
|
||||
uint32_t mask_flags; /* master MTD flags to mask out for this partition */
|
||||
struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/
|
||||
struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only) */
|
||||
};
|
||||
|
||||
#define MTDPART_OFS_NXTBLK (-2)
|
||||
|
|
@ -89,4 +89,9 @@ static inline int mtd_has_cmdlinepart(void) { return 1; }
|
|||
static inline int mtd_has_cmdlinepart(void) { return 0; }
|
||||
#endif
|
||||
|
||||
int mtd_is_master(struct mtd_info *mtd);
|
||||
int mtd_add_partition(struct mtd_info *master, char *name,
|
||||
long long offset, long long length);
|
||||
int mtd_del_partition(struct mtd_info *master, int partno);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue