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mmc: clarify DDR timing mode between SD-UHS and eMMC

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This change distinguishes DDR timing mode of current
mixed usage to clarify device type.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
This commit is contained in:
Seungwon Jeon 2014-03-14 21:11:56 +09:00 • committed by Chris Ball
parent a798c10faf
commit 79f7ae7c45
3 changed files with 6 additions and 2 deletions
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3
include/linux/mmc/host.h
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@ -58,7 +58,8 @@ struct mmc_ios {
#define MMC_TIMING_UHS_SDR50 5
#define MMC_TIMING_UHS_SDR104 6
#define MMC_TIMING_UHS_DDR50 7
#define MMC_TIMING_MMC_HS200 8
#define MMC_TIMING_MMC_DDR52 8
#define MMC_TIMING_MMC_HS200 9
#define MMC_SDR_MODE 0
#define MMC_1_2V_DDR_MODE 1