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MIPS: Make use of the ERETNC instruction on MIPS R6

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The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
one, except it does not clear the LLB bit in the LLADDR register.
This feature is necessary to safely emulate R2 LL/SC instructions.
However, on context switches, we need to clear the LLAddr/LLB bit
in order to make sure that an SC instruction from the new thread
will never succeed if it happens to interrupt an LL operation on the
same address from the previous thread.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras 2014-12-03 12:37:32 +00:00
parent b0a668fb20
commit 7c151d3d5d
5 changed files with 28 additions and 4 deletions
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9
arch/mips/include/asm/switch_to.h
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@ -75,9 +75,12 @@ do { \
#endif
#define __clear_software_ll_bit() \
do { \
if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
ll_bit = 0; \
do { if (cpu_has_rw_llb) { \
write_c0_lladdr(0); \
} else { \
if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)\
ll_bit = 0; \
} \
} while (0)
#define switch_to(prev, next, last) \