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https://github.com/Fishwaldo/Star64_linux.git
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MIPS: Add support for Texas Instruments AR7 System-on-a-Chip
This patch adds support for the Texas Instruments AR7 System-on-a-Chip. It supports the TNETD7100, 7200 and 7300 versions of the SoC. Signed-off-by: Matteo Croce <matteo@openwrt.org> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Eugene Konev <ejka@openwrt.org> Signed-off-by: Nicolas Thill <nico@openwrt.org> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Florian Fainelli
Ralf Baechle
parent
7c5371c403
commit
7ca5dc145b
18 changed files with 3307 additions and 0 deletions
178
arch/mips/include/asm/mach-ar7/ar7.h
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178
arch/mips/include/asm/mach-ar7/ar7.h
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/*
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* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __AR7_H__
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#define __AR7_H__
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <asm/addrspace.h>
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#define AR7_SDRAM_BASE 0x14000000
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#define AR7_REGS_BASE 0x08610000
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#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
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#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
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/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
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#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
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#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
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#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
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#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
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#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
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#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
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#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
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#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
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#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
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#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
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#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
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#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
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#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
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#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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#define AR7_RESET_PEREPHERIAL 0x0
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#define AR7_RESET_SOFTWARE 0x4
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#define AR7_RESET_STATUS 0x8
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#define AR7_RESET_BIT_CPMAC_LO 17
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#define AR7_RESET_BIT_CPMAC_HI 21
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#define AR7_RESET_BIT_MDIO 22
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#define AR7_RESET_BIT_EPHY 26
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/* GPIO control registers */
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#define AR7_GPIO_INPUT 0x0
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#define AR7_GPIO_OUTPUT 0x4
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#define AR7_GPIO_DIR 0x8
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#define AR7_GPIO_ENABLE 0xc
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#define AR7_CHIP_7100 0x18
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#define AR7_CHIP_7200 0x2b
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#define AR7_CHIP_7300 0x05
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/* Interrupts */
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#define AR7_IRQ_UART0 15
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#define AR7_IRQ_UART1 16
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/* Clocks */
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#define AR7_AFE_CLOCK 35328000
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#define AR7_REF_CLOCK 25000000
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#define AR7_XTAL_CLOCK 24000000
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struct plat_cpmac_data {
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int reset_bit;
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int power_bit;
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u32 phy_mask;
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char dev_addr[6];
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};
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struct plat_dsl_data {
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int reset_bit_dsl;
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int reset_bit_sar;
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};
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extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
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static inline u16 ar7_chip_id(void)
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{
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return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
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}
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static inline u8 ar7_chip_rev(void)
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{
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return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
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}
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static inline int ar7_cpu_freq(void)
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{
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return ar7_cpu_clock;
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}
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static inline int ar7_bus_freq(void)
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{
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return ar7_bus_clock;
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}
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static inline int ar7_vbus_freq(void)
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{
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return ar7_bus_clock / 2;
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}
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#define ar7_cpmac_freq ar7_vbus_freq
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static inline int ar7_dsp_freq(void)
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{
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return ar7_dsp_clock;
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}
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static inline int ar7_has_high_cpmac(void)
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{
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u16 chip_id = ar7_chip_id();
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switch (chip_id) {
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case AR7_CHIP_7100:
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case AR7_CHIP_7200:
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return 0;
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case AR7_CHIP_7300:
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return 1;
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default:
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return -ENXIO;
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}
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}
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#define ar7_has_high_vlynq ar7_has_high_cpmac
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#define ar7_has_second_uart ar7_has_high_cpmac
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static inline void ar7_device_enable(u32 bit)
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{
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void *reset_reg =
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(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
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writel(readl(reset_reg) | (1 << bit), reset_reg);
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msleep(20);
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}
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static inline void ar7_device_disable(u32 bit)
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{
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void *reset_reg =
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(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
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writel(readl(reset_reg) & ~(1 << bit), reset_reg);
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msleep(20);
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}
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static inline void ar7_device_reset(u32 bit)
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{
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ar7_device_disable(bit);
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ar7_device_enable(bit);
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}
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static inline void ar7_device_on(u32 bit)
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{
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void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
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writel(readl(power_reg) | (1 << bit), power_reg);
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msleep(20);
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}
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static inline void ar7_device_off(u32 bit)
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{
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void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
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writel(readl(power_reg) & ~(1 << bit), power_reg);
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msleep(20);
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}
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#endif /* __AR7_H__ */
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110
arch/mips/include/asm/mach-ar7/gpio.h
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110
arch/mips/include/asm/mach-ar7/gpio.h
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@ -0,0 +1,110 @@
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/*
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* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __AR7_GPIO_H__
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#define __AR7_GPIO_H__
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#include <asm/mach-ar7/ar7.h>
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#define AR7_GPIO_MAX 32
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extern int gpio_request(unsigned gpio, const char *label);
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extern void gpio_free(unsigned gpio);
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/* Common GPIO layer */
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static inline int gpio_get_value(unsigned gpio)
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{
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void __iomem *gpio_in =
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(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
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return readl(gpio_in) & (1 << gpio);
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}
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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void __iomem *gpio_out =
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(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
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unsigned tmp;
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tmp = readl(gpio_out) & ~(1 << gpio);
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if (value)
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tmp |= 1 << gpio;
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writel(tmp, gpio_out);
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}
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static inline int gpio_direction_input(unsigned gpio)
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{
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void __iomem *gpio_dir =
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(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
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if (gpio >= AR7_GPIO_MAX)
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return -EINVAL;
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writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
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return 0;
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}
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static inline int gpio_direction_output(unsigned gpio, int value)
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{
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void __iomem *gpio_dir =
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(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
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if (gpio >= AR7_GPIO_MAX)
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return -EINVAL;
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gpio_set_value(gpio, value);
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writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
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return 0;
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}
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static inline int gpio_to_irq(unsigned gpio)
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{
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return -EINVAL;
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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return -EINVAL;
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}
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/* Board specific GPIO functions */
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static inline int ar7_gpio_enable(unsigned gpio)
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{
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void __iomem *gpio_en =
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(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
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writel(readl(gpio_en) | (1 << gpio), gpio_en);
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return 0;
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}
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static inline int ar7_gpio_disable(unsigned gpio)
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{
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void __iomem *gpio_en =
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(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
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writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
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return 0;
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}
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#include <asm-generic/gpio.h>
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#endif
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16
arch/mips/include/asm/mach-ar7/irq.h
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16
arch/mips/include/asm/mach-ar7/irq.h
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Shamelessly copied from asm-mips/mach-emma2rh/
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* Copyright (C) 2003 by Ralf Baechle
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*/
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#ifndef __ASM_AR7_IRQ_H
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#define __ASM_AR7_IRQ_H
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#define NR_IRQS 256
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#include_next <irq.h>
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#endif /* __ASM_AR7_IRQ_H */
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25
arch/mips/include/asm/mach-ar7/prom.h
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25
arch/mips/include/asm/mach-ar7/prom.h
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@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __PROM_H__
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#define __PROM_H__
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extern char *prom_getenv(const char *name);
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extern void prom_meminit(void);
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#endif /* __PROM_H__ */
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22
arch/mips/include/asm/mach-ar7/spaces.h
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22
arch/mips/include/asm/mach-ar7/spaces.h
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
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* Copyright (C) 2000, 2002 Maciej W. Rozycki
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* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_AR7_SPACES_H
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#define _ASM_AR7_SPACES_H
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/*
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* This handles the memory map.
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* We handle pages at KSEG0 for kernels with 32 bit address space.
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*/
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#define PAGE_OFFSET 0x94000000UL
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#define PHYS_OFFSET 0x14000000UL
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#include <asm/mach-generic/spaces.h>
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#endif /* __ASM_AR7_SPACES_H */
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25
arch/mips/include/asm/mach-ar7/war.h
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25
arch/mips/include/asm/mach-ar7/war.h
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@ -0,0 +1,25 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MIPS_MACH_AR7_WAR_H
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#define __ASM_MIPS_MACH_AR7_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define RM9000_CDEX_SMP_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MIPS_MACH_AR7_WAR_H */
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