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drm/i915: Use the correct PCH transcoder for LPT/WPT in intel_sanitize_frame_start_delay()

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LPT/WPT only have PCH transcoder A. Make sure we poke at its
chicken register instead of some non-existent register when
FDI is being driven by pipe B or C.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191128182358.14477-1-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
This commit is contained in:
Ville Syrjälä 2019-11-28 20:23:58 +02:00
parent 1bbdd241ff
commit 7df49149b2
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/i915/display/intel_display.c
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@ -17272,7 +17272,8 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
val |= TRANS_FRAME_START_DELAY(0);
I915_WRITE(reg, val);
} else {
i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
u32 val;
val = I915_READ(reg);