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iwlwifi: pcie: get rid of q->n_bd
This variable always tracks a constant value (256) so there's no need to have it. Removing it simplifies code generation, reducing the .text size (by about 240 bytes on x86-64.) Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
This commit is contained in:
parent
6d6e68f839
commit
83f32a4b4a
4 changed files with 45 additions and 53 deletions
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@ -117,21 +117,19 @@ struct iwl_dma_ptr {
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/**
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/**
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* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
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* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
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* @index -- current index
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* @index -- current index
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* @n_bd -- total number of entries in queue (must be power of 2)
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*/
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*/
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static inline int iwl_queue_inc_wrap(int index, int n_bd)
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static inline int iwl_queue_inc_wrap(int index)
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{
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{
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return ++index & (n_bd - 1);
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return ++index & (TFD_QUEUE_SIZE_MAX - 1);
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}
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}
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/**
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/**
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* iwl_queue_dec_wrap - decrement queue index, wrap back to end
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* iwl_queue_dec_wrap - decrement queue index, wrap back to end
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* @index -- current index
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* @index -- current index
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* @n_bd -- total number of entries in queue (must be power of 2)
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*/
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*/
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static inline int iwl_queue_dec_wrap(int index, int n_bd)
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static inline int iwl_queue_dec_wrap(int index)
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{
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{
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return --index & (n_bd - 1);
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return --index & (TFD_QUEUE_SIZE_MAX - 1);
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}
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}
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struct iwl_cmd_meta {
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struct iwl_cmd_meta {
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@ -145,13 +143,13 @@ struct iwl_cmd_meta {
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*
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*
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* Contains common data for Rx and Tx queues.
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* Contains common data for Rx and Tx queues.
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*
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*
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* Note the difference between n_bd and n_window: the hardware
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* Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
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* always assumes 256 descriptors, so n_bd is always 256 (unless
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* always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
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* there might be HW changes in the future). For the normal TX
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* there might be HW changes in the future). For the normal TX
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* queues, n_window, which is the size of the software queue data
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* queues, n_window, which is the size of the software queue data
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* is also 256; however, for the command queue, n_window is only
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* is also 256; however, for the command queue, n_window is only
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* 32 since we don't need so many commands pending. Since the HW
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, n_bd stays 256. As a result,
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* still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result,
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* the software buffers (in the variables @meta, @txb in struct
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* the software buffers (in the variables @meta, @txb in struct
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* iwl_txq) only have 32 entries, while the HW buffers (@tfds in
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* iwl_txq) only have 32 entries, while the HW buffers (@tfds in
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* the same struct) have 256.
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* the same struct) have 256.
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@ -162,7 +160,6 @@ struct iwl_cmd_meta {
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* data is a window overlayed over the HW queue.
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* data is a window overlayed over the HW queue.
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*/
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*/
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struct iwl_queue {
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struct iwl_queue {
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int n_bd; /* number of BDs in this queue */
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int write_ptr; /* 1-st empty entry (index) host_w*/
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int write_ptr; /* 1-st empty entry (index) host_w*/
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int read_ptr; /* last used entry (index) host_r*/
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int read_ptr; /* last used entry (index) host_r*/
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/* use for monitoring and recovering the stuck queue */
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/* use for monitoring and recovering the stuck queue */
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@ -850,7 +850,7 @@ static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
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trans_pcie->ict_index, read);
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trans_pcie->ict_index, read);
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trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
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trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
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trans_pcie->ict_index =
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trans_pcie->ict_index =
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iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
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((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
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read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
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read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
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trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
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trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
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@ -1337,8 +1337,8 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
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IWL_ERR(trans,
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IWL_ERR(trans,
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"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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cnt, active ? "" : "in", fifo, tbl_dw,
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cnt, active ? "" : "in", fifo, tbl_dw,
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iwl_read_prph(trans,
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iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
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SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
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(TFD_QUEUE_SIZE_MAX - 1),
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iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
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iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
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}
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}
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@ -70,20 +70,20 @@ static int iwl_queue_space(const struct iwl_queue *q)
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/*
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/*
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* To avoid ambiguity between empty and completely full queues, there
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* To avoid ambiguity between empty and completely full queues, there
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* should always be less than q->n_bd elements in the queue.
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* should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
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* If q->n_window is smaller than q->n_bd, there is no need to reserve
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* If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
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* any queue entries for this purpose.
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* to reserve any queue entries for this purpose.
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*/
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*/
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if (q->n_window < q->n_bd)
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if (q->n_window < TFD_QUEUE_SIZE_MAX)
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max = q->n_window;
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max = q->n_window;
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else
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else
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max = q->n_bd - 1;
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max = TFD_QUEUE_SIZE_MAX - 1;
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/*
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/*
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* q->n_bd is a power of 2, so the following is equivalent to modulo by
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* TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
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* q->n_bd and is well defined for negative dividends.
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* modulo by TFD_QUEUE_SIZE_MAX and is well defined.
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*/
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*/
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used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1);
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used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
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if (WARN_ON(used > max))
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if (WARN_ON(used > max))
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return 0;
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return 0;
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@ -94,17 +94,11 @@ static int iwl_queue_space(const struct iwl_queue *q)
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/*
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/*
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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*/
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*/
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static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
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static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
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{
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{
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q->n_bd = count;
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q->n_window = slots_num;
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q->n_window = slots_num;
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q->id = id;
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q->id = id;
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/* count must be power-of-two size, otherwise iwl_queue_inc_wrap
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* and iwl_queue_dec_wrap are broken. */
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if (WARN_ON(!is_power_of_2(count)))
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return -EINVAL;
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/* slots_num must be power-of-two size, otherwise
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/* slots_num must be power-of-two size, otherwise
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* get_cmd_index is broken. */
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* get_cmd_index is broken. */
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if (WARN_ON(!is_power_of_2(slots_num)))
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if (WARN_ON(!is_power_of_2(slots_num)))
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@ -197,13 +191,13 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
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IWL_ERR(trans,
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IWL_ERR(trans,
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"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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i, active ? "" : "in", fifo, tbl_dw,
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i, active ? "" : "in", fifo, tbl_dw,
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iwl_read_prph(trans,
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iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
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SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
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(TFD_QUEUE_SIZE_MAX - 1),
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iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
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iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
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}
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}
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for (i = q->read_ptr; i != q->write_ptr;
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for (i = q->read_ptr; i != q->write_ptr;
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i = iwl_queue_inc_wrap(i, q->n_bd))
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i = iwl_queue_inc_wrap(i))
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IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
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IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
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le32_to_cpu(txq->scratchbufs[i].scratch));
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le32_to_cpu(txq->scratchbufs[i].scratch));
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@ -425,13 +419,17 @@ static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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{
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{
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struct iwl_tfd *tfd_tmp = txq->tfds;
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struct iwl_tfd *tfd_tmp = txq->tfds;
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/* rd_ptr is bounded by n_bd and idx is bounded by n_window */
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/* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
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* idx is bounded by n_window
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*/
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int rd_ptr = txq->q.read_ptr;
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int rd_ptr = txq->q.read_ptr;
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int idx = get_cmd_index(&txq->q, rd_ptr);
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int idx = get_cmd_index(&txq->q, rd_ptr);
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lockdep_assert_held(&txq->lock);
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lockdep_assert_held(&txq->lock);
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/* We have only q->n_window txq->entries, but we use q->n_bd tfds */
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/* We have only q->n_window txq->entries, but we use
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* TFD_QUEUE_SIZE_MAX tfds
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*/
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iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
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iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
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/* free SKB */
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/* free SKB */
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@ -565,8 +563,7 @@ static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
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BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
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BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
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/* Initialize queue's high/low-water marks, and head/tail indexes */
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/* Initialize queue's high/low-water marks, and head/tail indexes */
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ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
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ret = iwl_queue_init(&txq->q, slots_num, txq_id);
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txq_id);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -591,15 +588,12 @@ static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
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struct iwl_txq *txq = &trans_pcie->txq[txq_id];
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struct iwl_txq *txq = &trans_pcie->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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struct iwl_queue *q = &txq->q;
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if (!q->n_bd)
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return;
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spin_lock_bh(&txq->lock);
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spin_lock_bh(&txq->lock);
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while (q->write_ptr != q->read_ptr) {
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while (q->write_ptr != q->read_ptr) {
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IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
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IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
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txq_id, q->read_ptr);
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txq_id, q->read_ptr);
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iwl_pcie_txq_free_tfd(trans, txq);
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iwl_pcie_txq_free_tfd(trans, txq);
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
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}
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}
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txq->active = false;
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txq->active = false;
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spin_unlock_bh(&txq->lock);
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spin_unlock_bh(&txq->lock);
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@ -636,10 +630,12 @@ static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
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}
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}
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/* De-alloc circular buffer of TFDs */
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd) {
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if (txq->tfds) {
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dma_free_coherent(dev, sizeof(struct iwl_tfd) *
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dma_free_coherent(dev,
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txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
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txq->tfds, txq->q.dma_addr);
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txq->q.dma_addr = 0;
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txq->q.dma_addr = 0;
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txq->tfds = NULL;
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dma_free_coherent(dev,
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dma_free_coherent(dev,
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sizeof(*txq->scratchbufs) * txq->q.n_window,
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sizeof(*txq->scratchbufs) * txq->q.n_window,
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@ -948,8 +944,7 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_txq *txq = &trans_pcie->txq[txq_id];
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struct iwl_txq *txq = &trans_pcie->txq[txq_id];
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/* n_bd is usually 256 => n_bd - 1 = 0xff */
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int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
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int tfd_num = ssn & (txq->q.n_bd - 1);
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struct iwl_queue *q = &txq->q;
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struct iwl_queue *q = &txq->q;
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int last_to_free;
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int last_to_free;
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@ -973,12 +968,12 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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/*Since we free until index _not_ inclusive, the one before index is
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/*Since we free until index _not_ inclusive, the one before index is
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* the last we will free. This one must be used */
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* the last we will free. This one must be used */
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last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
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last_to_free = iwl_queue_dec_wrap(tfd_num);
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if (!iwl_queue_used(q, last_to_free)) {
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if (!iwl_queue_used(q, last_to_free)) {
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IWL_ERR(trans,
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IWL_ERR(trans,
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"%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
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"%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
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__func__, txq_id, last_to_free, q->n_bd,
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__func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
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q->write_ptr, q->read_ptr);
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q->write_ptr, q->read_ptr);
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goto out;
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goto out;
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}
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}
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@ -988,7 +983,7 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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for (;
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for (;
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q->read_ptr != tfd_num;
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q->read_ptr != tfd_num;
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
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if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
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if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
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continue;
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continue;
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@ -1027,16 +1022,16 @@ static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
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lockdep_assert_held(&txq->lock);
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lockdep_assert_held(&txq->lock);
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if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
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if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
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IWL_ERR(trans,
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IWL_ERR(trans,
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"%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
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"%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
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__func__, txq_id, idx, q->n_bd,
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__func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
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q->write_ptr, q->read_ptr);
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q->write_ptr, q->read_ptr);
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return;
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return;
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}
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}
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for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
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for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
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if (nfreed++ > 0) {
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if (nfreed++ > 0) {
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IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
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IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
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@ -1445,7 +1440,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Increment and update queue's write index */
|
/* Increment and update queue's write index */
|
||||||
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
|
||||||
iwl_pcie_txq_inc_wr_ptr(trans, txq);
|
iwl_pcie_txq_inc_wr_ptr(trans, txq);
|
||||||
|
|
||||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||||
|
@ -1788,7 +1783,7 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
||||||
mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
|
mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
|
||||||
|
|
||||||
/* Tell device the write index *just past* this latest filled TFD */
|
/* Tell device the write index *just past* this latest filled TFD */
|
||||||
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
|
||||||
if (!wait_write_ptr)
|
if (!wait_write_ptr)
|
||||||
iwl_pcie_txq_inc_wr_ptr(trans, txq);
|
iwl_pcie_txq_inc_wr_ptr(trans, txq);
|
||||||
|
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue