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PCI: qcom: Fix the incorrect register usage in v2.7.0 config
commit2542e16c39
upstream. Qcom PCIe IP version v2.7.0 and its derivatives don't contain the PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT register. Instead, they have the new PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register. So fix the incorrect register usage which is modifying a different register. Also in this IP version, this register change doesn't depend on MSI being enabled. So remove that check also. Link: https://lore.kernel.org/r/20230316081117.14288-2-manivannan.sadhasivam@linaro.org Fixes:ed8cc3b1fc
("PCI: qcom: Add support for SDM845 PCIe controller") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: <stable@vger.kernel.org> # 5.6+ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 3 additions and 5 deletions
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@ -1228,11 +1228,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
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val |= BIT(4);
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writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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val |= BIT(31);
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writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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}
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val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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val |= BIT(31);
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writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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return 0;
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err_disable_clocks:
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