From 84ee4f56b3d5e7180ca6c66f7d76593b0c38753d Mon Sep 17 00:00:00 2001
From: Tom <support@vamrs.com>
Date: Fri, 8 Jan 2021 02:59:40 +0800
Subject: [PATCH] riscv/starfive: Add VIC7100 support

---
 arch/riscv/Kconfig.socs        | 50 ++++++++++++++++++++++++++++++++++
 include/soc/starfive/vic7100.h | 36 ++++++++++++++++++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 include/soc/starfive/vic7100.h

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index ed963761fbd2..81cd35b02d55 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -18,6 +18,56 @@ config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config SOC_STARFIVE_VIC7100
+	bool "StarFive VIC7100 SoC"
+	select SOC_SIFIVE
+	select OF_RESERVED_MEM
+	select SIFIVE_L2
+	select SIFIVE_L2_FLUSH
+	select DW_AXI_DMAC_STARFIVE
+	select GPIO_STARFIVE_VIC
+	select HW_RANDOM_STARFIVE_VIC
+	help
+	  This enables support for StarFive VIC7100 SoC Platform Hardware.
+
+menu "StarFive VIC7100 SoC Debug Option"
+	depends on SOC_STARFIVE_VIC7100
+
+config FPGA_GMAC_FLUSH_DDR
+	bool "VIC7100 SOC GMAC description and packet buffer flush"
+	depends on SOC_STARFIVE_VIC7100
+	depends on STMMAC_ETH
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 GMAC description and packet buffer flush
+
+config MMC_DW_FLUSH_DDR
+	bool "VIC7100 SOC DW MMC buffer flush"
+	depends on SOC_STARFIVE_VIC7100
+	depends on MMC_DW
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 DW MMC description and data buffer flush
+
+config USB_CDNS3_HOST_FLUSH_DMA
+	bool "Cadence USB3 host controller flush dma memery"
+	depends on USB
+	depends on USB_CDNS3
+	depends on SOC_STARFIVE_VIC7100
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 DW USB CDNS3 driver data buffer flush
+
+config SOC_STARFIVE_VIC7100_I2C_GPIO
+	bool "VIC7100 SOC I2C GPIO init"
+	depends on I2C_DESIGNWARE_CORE
+	depends on SOC_STARFIVE_VIC7100
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 DW I2C GPIO init in Synopsys DesignWare master driver
+
+endmenu
+
 config SOC_VIRT
 	bool "QEMU Virt Machine"
 	select CLINT_TIMER if RISCV_M_MODE
diff --git a/include/soc/starfive/vic7100.h b/include/soc/starfive/vic7100.h
new file mode 100644
index 000000000000..a850f4cd11bf
--- /dev/null
+++ b/include/soc/starfive/vic7100.h
@@ -0,0 +1,36 @@
+#ifndef STARFIVE_VIC7100_H
+#define STARFIVE_VIC7100_H
+#include <asm/io.h>
+#include <soc/sifive/sifive_l2_cache.h>
+
+/*cache.c*/
+#define starfive_flush_dcache(start, len) \
+	sifive_l2_flush64_range(start, len)
+
+/*dma*/
+#define CONFIG_DW_DEBUG
+
+#define DMA_PRINTK(fmt,...) \
+	printk("[DW_DMA] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
+
+#ifdef CONFIG_DW_DEBUG
+#define DMA_DEBUG(fmt,...) \
+	printk("[DW_DMA_DEBUG] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
+#else
+#define DMA_BEBUG(fmt,...)
+#endif
+
+#define _dw_virt_to_phys(vaddr) (pfn_to_phys(virt_to_pfn(vaddr)))
+#define _dw_phys_to_virt(paddr) (page_to_virt(phys_to_page(paddr)))
+
+void *dw_phys_to_virt(u64 phys);
+u64 dw_virt_to_phys(void *vaddr);
+
+int dw_dma_async_do_memcpy(void *src, void *dst, size_t size);
+int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size);
+int dw_dma_memcpy(void *src, void *dst, size_t size);
+
+int dw_dma_mem2mem_arry(void);
+int dw_dma_mem2mem_test(void);
+
+#endif /*STARFIVE_VIC7100_H*/
\ No newline at end of file