mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-03-16 04:04:06 +00:00
Stable update
This commit is contained in:
Fedora Kernel Team
Fu Wei
parent
2c85ebc57b
commit
89362d1761
889 changed files with 6896 additions and 4343 deletions
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@ -5663,6 +5663,7 @@
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device);
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j = NO_REPORT_LUNS (don't use report luns
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command, uas only);
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k = NO_SAME (do not use WRITE_SAME, uas only)
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l = NOT_LOCKABLE (don't try to lock and
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unlock ejectable media, not on uas);
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m = MAX_SECTORS_64 (don't transfer more
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@ -63,6 +63,11 @@ properties:
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description:
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Enables wake up of host system on alarm.
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reset-source:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The RTC is able to reset the machine.
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additionalProperties: true
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...
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@ -273,6 +273,24 @@ Contact: Daniel Vetter, Noralf Tronnes
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Level: Advanced
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Garbage collect fbdev scrolling acceleration
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--------------------------------------------
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Scroll acceleration is disabled in fbcon by hard-wiring p->scrollmode =
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SCROLL_REDRAW. There's a ton of code this will allow us to remove:
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- lots of code in fbcon.c
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- a bunch of the hooks in fbcon_ops, maybe the remaining hooks could be called
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directly instead of the function table (with a switch on p->rotate)
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- fb_copyarea is unused after this, and can be deleted from all drivers
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Note that not all acceleration code can be deleted, since clearing and cursor
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support is still accelerated, which might be good candidates for further
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deletion projects.
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Contact: Daniel Vetter
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Level: Intermediate
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idr_init_base()
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---------------
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@ -89,7 +89,7 @@ Read path::
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.. _seqcount_locktype_t:
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Sequence counters with associated locks (``seqcount_LOCKTYPE_t``)
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Sequence counters with associated locks (``seqcount_LOCKNAME_t``)
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-----------------------------------------------------------------
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As discussed at :ref:`seqcount_t`, sequence count write side critical
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@ -115,27 +115,26 @@ The following sequence counters with associated locks are defined:
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- ``seqcount_mutex_t``
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- ``seqcount_ww_mutex_t``
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The plain seqcount read and write APIs branch out to the specific
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seqcount_LOCKTYPE_t implementation at compile-time. This avoids kernel
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API explosion per each new seqcount LOCKTYPE.
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The sequence counter read and write APIs can take either a plain
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seqcount_t or any of the seqcount_LOCKNAME_t variants above.
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Initialization (replace "LOCKTYPE" with one of the supported locks)::
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Initialization (replace "LOCKNAME" with one of the supported locks)::
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/* dynamic */
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seqcount_LOCKTYPE_t foo_seqcount;
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seqcount_LOCKTYPE_init(&foo_seqcount, &lock);
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seqcount_LOCKNAME_t foo_seqcount;
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seqcount_LOCKNAME_init(&foo_seqcount, &lock);
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/* static */
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static seqcount_LOCKTYPE_t foo_seqcount =
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SEQCNT_LOCKTYPE_ZERO(foo_seqcount, &lock);
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static seqcount_LOCKNAME_t foo_seqcount =
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SEQCNT_LOCKNAME_ZERO(foo_seqcount, &lock);
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/* C99 struct init */
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struct {
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.seq = SEQCNT_LOCKTYPE_ZERO(foo.seq, &lock),
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.seq = SEQCNT_LOCKNAME_ZERO(foo.seq, &lock),
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} foo;
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Write path: same as in :ref:`seqcount_t`, while running from a context
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with the associated LOCKTYPE lock acquired.
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with the associated write serialization lock acquired.
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Read path: same as in :ref:`seqcount_t`.
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@ -41,6 +41,8 @@ Package
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Packages contain a number of cores plus shared resources, e.g. DRAM
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controller, shared caches etc.
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Modern systems may also use the term 'Die' for package.
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AMD nomenclature for package is 'Node'.
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Package-related topology information in the kernel:
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@ -53,11 +55,18 @@ Package-related topology information in the kernel:
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The number of dies in a package. This information is retrieved via CPUID.
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- cpuinfo_x86.cpu_die_id:
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The physical ID of the die. This information is retrieved via CPUID.
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- cpuinfo_x86.phys_proc_id:
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The physical ID of the package. This information is retrieved via CPUID
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and deduced from the APIC IDs of the cores in the package.
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Modern systems use this value for the socket. There may be multiple
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packages within a socket. This value may differ from cpu_die_id.
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- cpuinfo_x86.logical_proc_id:
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The logical ID of the package. As we do not trust BIOSes to enumerate the
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2
Makefile
2
Makefile
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 10
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SUBLEVEL = 0
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SUBLEVEL = 6
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EXTRAVERSION =
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NAME = Kleptomaniac Octopus
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16
arch/Kconfig
16
arch/Kconfig
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@ -143,6 +143,22 @@ config UPROBES
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managed by the kernel and kept transparent to the probed
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application. )
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config HAVE_64BIT_ALIGNED_ACCESS
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def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS
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help
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Some architectures require 64 bit accesses to be 64 bit
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aligned, which also requires structs containing 64 bit values
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to be 64 bit aligned too. This includes some 32 bit
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architectures which can do 64 bit accesses, as well as 64 bit
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architectures without unaligned access.
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This symbol should be selected by an architecture if 64 bit
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accesses are required to be 64 bit aligned in this way even
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though it is not a 64 bit architecture.
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See Documentation/unaligned-memory-access.txt for more
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information on the topic of unaligned memory accesses.
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config HAVE_EFFICIENT_UNALIGNED_ACCESS
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bool
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help
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@ -116,7 +116,7 @@
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/*
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* Debug print of the final appended DTB location
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*/
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.macro dbgadtb, begin, end
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.macro dbgadtb, begin, size
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#ifdef DEBUG
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kputc #'D'
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kputc #'T'
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@ -129,7 +129,7 @@
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kputc #'('
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kputc #'0'
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kputc #'x'
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kphex \end, 8 /* End of appended DTB */
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kphex \size, 8 /* Size of appended DTB */
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kputc #')'
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kputc #'\n'
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#endif
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@ -266,11 +266,6 @@
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reg = <0x11000 0x100>;
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};
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&i2c1 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x100>;
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};
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&mpic {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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@ -82,11 +82,6 @@
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status = "okay";
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};
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&vuart {
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// VUART Host Console
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status = "okay";
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};
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&uart1 {
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// Host Console
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status = "okay";
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@ -22,9 +22,9 @@
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#size-cells = <1>;
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ranges;
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vga_memory: framebuffer@7f000000 {
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vga_memory: framebuffer@9f000000 {
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no-map;
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reg = <0x7f000000 0x01000000>;
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reg = <0x9f000000 0x01000000>; /* 16M */
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};
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};
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@ -26,7 +26,7 @@
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#size-cells = <1>;
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ranges;
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flash_memory: region@ba000000 {
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flash_memory: region@b8000000 {
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no-map;
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reg = <0xb8000000 0x4000000>; /* 64M */
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};
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@ -357,7 +357,7 @@
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#gpio-cells = <2>;
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gpio-controller;
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compatible = "aspeed,ast2600-gpio";
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reg = <0x1e780000 0x800>;
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reg = <0x1e780000 0x400>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 0 208>;
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ngpios = <208>;
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@ -569,11 +569,14 @@
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atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
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};
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};
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}; /* pinctrl */
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&pmc {
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atmel,osc-bypass;
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};
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usb1 {
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pinctrl_usb_default: usb_default {
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atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
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AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
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};
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};
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}; /* pinctrl */
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&pwm0 {
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pinctrl-names = "default";
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@ -684,6 +687,8 @@
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atmel,vbus-gpio = <0
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&pioD 15 GPIO_ACTIVE_HIGH
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&pioD 16 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_default>;
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status = "okay";
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};
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@ -242,6 +242,11 @@
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atmel,pins =
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<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
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};
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pinctrl_usb_default: usb_default {
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atmel,pins =
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<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
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AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
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};
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};
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};
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};
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@ -259,6 +264,8 @@
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&pioE 3 GPIO_ACTIVE_LOW
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&pioE 4 GPIO_ACTIVE_LOW
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>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_default>;
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status = "okay";
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};
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@ -134,6 +134,11 @@
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atmel,pins =
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<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
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};
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pinctrl_usb_default: usb_default {
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atmel,pins =
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<AT91_PIOE 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
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AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
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};
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pinctrl_key_gpio: key_gpio_0 {
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atmel,pins =
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<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
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@ -159,6 +164,8 @@
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&pioE 11 GPIO_ACTIVE_HIGH
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&pioE 14 GPIO_ACTIVE_HIGH
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>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_default>;
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status = "okay";
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};
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|
|
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@ -282,23 +282,26 @@
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atmel,adc-use-res = "highres";
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trigger0 {
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trigger-name = "timer-counter-0";
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trigger-name = "external-rising";
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trigger-value = <0x1>;
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trigger-external;
|
||||
};
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||||
|
||||
trigger1 {
|
||||
trigger-name = "timer-counter-1";
|
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trigger-value = <0x3>;
|
||||
trigger-name = "external-falling";
|
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trigger-value = <0x2>;
|
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trigger-external;
|
||||
};
|
||||
|
||||
trigger2 {
|
||||
trigger-name = "timer-counter-2";
|
||||
trigger-value = <0x5>;
|
||||
trigger-name = "external-any";
|
||||
trigger-value = <0x3>;
|
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trigger-external;
|
||||
};
|
||||
|
||||
trigger3 {
|
||||
trigger-name = "external";
|
||||
trigger-value = <0x13>;
|
||||
trigger-external;
|
||||
trigger-name = "continuous";
|
||||
trigger-value = <0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
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|||
|
|
@ -327,6 +327,8 @@
|
|||
regulator-name = "vddq_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
/* Supplies also GPK and GPJ */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
|
|
@ -637,11 +639,11 @@
|
|||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "peripheral";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
|
|
|
|||
|
|
@ -560,6 +560,34 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
usb3_1_oc: usb3-1-oc {
|
||||
samsung,pins = "gpk2-4", "gpk2-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3_1_vbusctrl: usb3-1-vbusctrl {
|
||||
samsung,pins = "gpk2-6", "gpk2-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3_0_oc: usb3-0-oc {
|
||||
samsung,pins = "gpk3-0", "gpk3-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3_0_vbusctrl: usb3-0-vbusctrl {
|
||||
samsung,pins = "gpk3-2", "gpk3-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_2 {
|
||||
|
|
|
|||
|
|
@ -390,6 +390,8 @@
|
|||
&usbdrd3_0 {
|
||||
clocks = <&clock CLK_USBD300>;
|
||||
clock-names = "usbdrd30";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>;
|
||||
};
|
||||
|
||||
&usbdrd_phy0 {
|
||||
|
|
@ -401,6 +403,8 @@
|
|||
&usbdrd3_1 {
|
||||
clocks = <&clock CLK_USBD301>;
|
||||
clock-names = "usbdrd30";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>;
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
button_pins: pinmux_button_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
|
||||
OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -656,6 +656,7 @@
|
|||
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
no-memory-wc;
|
||||
ranges = <0 0xf8044000 0x1420>;
|
||||
};
|
||||
|
||||
|
|
@ -724,7 +725,7 @@
|
|||
|
||||
can0: can@f8054000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
|
||||
reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
|
||||
<64 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
|
|
@ -1130,7 +1131,7 @@
|
|||
|
||||
can1: can@fc050000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
|
||||
reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
|
||||
<65 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
|
|
@ -1140,7 +1141,7 @@
|
|||
assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
|
||||
bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
#include "tegra20-cpu-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra20 Ventana evaluation board";
|
||||
|
|
@ -592,6 +593,16 @@
|
|||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu0: cpu@0 {
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
|
|||
|
|
@ -386,20 +386,32 @@ ENTRY(ce_aes_ctr_encrypt)
|
|||
.Lctrloop4x:
|
||||
subs r4, r4, #4
|
||||
bmi .Lctr1x
|
||||
add r6, r6, #1
|
||||
|
||||
/*
|
||||
* NOTE: the sequence below has been carefully tweaked to avoid
|
||||
* a silicon erratum that exists in Cortex-A57 (#1742098) and
|
||||
* Cortex-A72 (#1655431) cores, where AESE/AESMC instruction pairs
|
||||
* may produce an incorrect result if they take their input from a
|
||||
* register of which a single 32-bit lane has been updated the last
|
||||
* time it was modified. To work around this, the lanes of registers
|
||||
* q0-q3 below are not manipulated individually, and the different
|
||||
* counter values are prepared by successive manipulations of q7.
|
||||
*/
|
||||
add ip, r6, #1
|
||||
vmov q0, q7
|
||||
rev ip, ip
|
||||
add lr, r6, #2
|
||||
vmov s31, ip @ set lane 3 of q1 via q7
|
||||
add ip, r6, #3
|
||||
rev lr, lr
|
||||
vmov q1, q7
|
||||
rev ip, r6
|
||||
add r6, r6, #1
|
||||
vmov s31, lr @ set lane 3 of q2 via q7
|
||||
rev ip, ip
|
||||
vmov q2, q7
|
||||
vmov s7, ip
|
||||
rev ip, r6
|
||||
add r6, r6, #1
|
||||
vmov s31, ip @ set lane 3 of q3 via q7
|
||||
add r6, r6, #4
|
||||
vmov q3, q7
|
||||
vmov s11, ip
|
||||
rev ip, r6
|
||||
add r6, r6, #1
|
||||
vmov s15, ip
|
||||
|
||||
vld1.8 {q4-q5}, [r1]!
|
||||
vld1.8 {q6}, [r1]!
|
||||
vld1.8 {q15}, [r1]!
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
|
|||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
MODULE_ALIAS_CRYPTO("ecb(aes)");
|
||||
MODULE_ALIAS_CRYPTO("cbc(aes)");
|
||||
MODULE_ALIAS_CRYPTO("cbc(aes)-all");
|
||||
MODULE_ALIAS_CRYPTO("ctr(aes)");
|
||||
MODULE_ALIAS_CRYPTO("xts(aes)");
|
||||
|
||||
|
|
@ -191,7 +191,8 @@ static int cbc_init(struct crypto_skcipher *tfm)
|
|||
struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
|
||||
unsigned int reqsize;
|
||||
|
||||
ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
|
||||
ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC |
|
||||
CRYPTO_ALG_NEED_FALLBACK);
|
||||
if (IS_ERR(ctx->enc_tfm))
|
||||
return PTR_ERR(ctx->enc_tfm);
|
||||
|
||||
|
|
@ -441,7 +442,8 @@ static struct skcipher_alg aes_algs[] = { {
|
|||
.base.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx),
|
||||
.base.cra_module = THIS_MODULE,
|
||||
.base.cra_flags = CRYPTO_ALG_INTERNAL,
|
||||
.base.cra_flags = CRYPTO_ALG_INTERNAL |
|
||||
CRYPTO_ALG_NEED_FALLBACK,
|
||||
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
|
|
|
|||
|
|
@ -252,31 +252,10 @@ __und_svc:
|
|||
#else
|
||||
svc_entry
|
||||
#endif
|
||||
@
|
||||
@ call emulation code, which returns using r9 if it has emulated
|
||||
@ the instruction, or the more conventional lr if we are to treat
|
||||
@ this as a real undefined instruction
|
||||
@
|
||||
@ r0 - instruction
|
||||
@
|
||||
#ifndef CONFIG_THUMB2_KERNEL
|
||||
ldr r0, [r4, #-4]
|
||||
#else
|
||||
mov r1, #2
|
||||
ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
|
||||
cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
|
||||
blo __und_svc_fault
|
||||
ldrh r9, [r4] @ bottom 16 bits
|
||||
add r4, r4, #2
|
||||
str r4, [sp, #S_PC]
|
||||
orr r0, r9, r0, lsl #16
|
||||
#endif
|
||||
badr r9, __und_svc_finish
|
||||
mov r2, r4
|
||||
bl call_fpe
|
||||
|
||||
mov r1, #4 @ PC correction to apply
|
||||
__und_svc_fault:
|
||||
THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode?
|
||||
THUMB( movne r1, #2 ) @ if so, fix up PC correction
|
||||
mov r0, sp @ struct pt_regs *regs
|
||||
bl __und_fault
|
||||
|
||||
|
|
|
|||
|
|
@ -671,12 +671,8 @@ ARM_BE8(rev16 ip, ip)
|
|||
ldrcc r7, [r4], #4 @ use branch for delay slot
|
||||
bcc 1b
|
||||
bx lr
|
||||
#else
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
|
||||
#else
|
||||
moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
|
||||
#endif
|
||||
b 2f
|
||||
1: ldr ip, [r7, r3]
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
|
|
@ -685,7 +681,7 @@ ARM_BE8(rev16 ip, ip)
|
|||
tst ip, #0x000f0000 @ check the rotation field
|
||||
orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
|
||||
biceq ip, ip, #0x00004000 @ clear bit 22
|
||||
orreq ip, ip, r0 @ mask in offset bits 7-0
|
||||
orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
|
||||
#else
|
||||
bic ip, ip, #0x000000ff
|
||||
tst ip, #0xf00 @ check the rotation field
|
||||
|
|
|
|||
|
|
@ -37,20 +37,3 @@ ENDPROC(vfp_null_entry)
|
|||
.align 2
|
||||
.LCvfp:
|
||||
.word vfp_vector
|
||||
|
||||
@ This code is called if the VFP does not exist. It needs to flag the
|
||||
@ failure to the VFP initialisation code.
|
||||
|
||||
__INIT
|
||||
ENTRY(vfp_testing_entry)
|
||||
dec_preempt_count_ti r10, r4
|
||||
ldr r0, VFP_arch_address
|
||||
str r0, [r0] @ set to non-zero value
|
||||
ret r9 @ we have handled the fault
|
||||
ENDPROC(vfp_testing_entry)
|
||||
|
||||
.align 2
|
||||
VFP_arch_address:
|
||||
.word VFP_arch
|
||||
|
||||
__FINIT
|
||||
|
|
|
|||
|
|
@ -79,11 +79,6 @@ ENTRY(vfp_support_entry)
|
|||
DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
|
||||
|
||||
.fpu vfpv2
|
||||
ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions
|
||||
and r3, r3, #MODE_MASK @ are supported in kernel mode
|
||||
teq r3, #USR_MODE
|
||||
bne vfp_kmode_exception @ Returns through lr
|
||||
|
||||
VFPFMRX r1, FPEXC @ Is the VFP enabled?
|
||||
DBGSTR1 "fpexc %08x", r1
|
||||
tst r1, #FPEXC_EN
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <asm/cputype.h>
|
||||
#include <asm/system_info.h>
|
||||
#include <asm/thread_notify.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/vfp.h>
|
||||
|
||||
#include "vfpinstr.h"
|
||||
|
|
@ -31,7 +32,6 @@
|
|||
/*
|
||||
* Our undef handlers (in entry.S)
|
||||
*/
|
||||
asmlinkage void vfp_testing_entry(void);
|
||||
asmlinkage void vfp_support_entry(void);
|
||||
asmlinkage void vfp_null_entry(void);
|
||||
|
||||
|
|
@ -42,7 +42,7 @@ asmlinkage void (*vfp_vector)(void) = vfp_null_entry;
|
|||
* Used in startup: set to non-zero if VFP checks fail
|
||||
* After startup, holds VFP architecture
|
||||
*/
|
||||
unsigned int VFP_arch;
|
||||
static unsigned int __initdata VFP_arch;
|
||||
|
||||
/*
|
||||
* The pointer to the vfpstate structure of the thread which currently
|
||||
|
|
@ -436,7 +436,7 @@ static void vfp_enable(void *unused)
|
|||
* present on all CPUs within a SMP complex. Needs to be called prior to
|
||||
* vfp_init().
|
||||
*/
|
||||
void vfp_disable(void)
|
||||
void __init vfp_disable(void)
|
||||
{
|
||||
if (VFP_arch) {
|
||||
pr_debug("%s: should be called prior to vfp_init\n", __func__);
|
||||
|
|
@ -642,7 +642,9 @@ static int vfp_starting_cpu(unsigned int unused)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void vfp_kmode_exception(void)
|
||||
#ifdef CONFIG_KERNEL_MODE_NEON
|
||||
|
||||
static int vfp_kmode_exception(struct pt_regs *regs, unsigned int instr)
|
||||
{
|
||||
/*
|
||||
* If we reach this point, a floating point exception has been raised
|
||||
|
|
@ -660,9 +662,51 @@ void vfp_kmode_exception(void)
|
|||
pr_crit("BUG: unsupported FP instruction in kernel mode\n");
|
||||
else
|
||||
pr_crit("BUG: FP instruction issued in kernel mode with FP unit disabled\n");
|
||||
pr_crit("FPEXC == 0x%08x\n", fmrx(FPEXC));
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KERNEL_MODE_NEON
|
||||
static struct undef_hook vfp_kmode_exception_hook[] = {{
|
||||
.instr_mask = 0xfe000000,
|
||||
.instr_val = 0xf2000000,
|
||||
.cpsr_mask = MODE_MASK | PSR_T_BIT,
|
||||
.cpsr_val = SVC_MODE,
|
||||
.fn = vfp_kmode_exception,
|
||||
}, {
|
||||
.instr_mask = 0xff100000,
|
||||
.instr_val = 0xf4000000,
|
||||
.cpsr_mask = MODE_MASK | PSR_T_BIT,
|
||||
.cpsr_val = SVC_MODE,
|
||||
.fn = vfp_kmode_exception,
|
||||
}, {
|
||||
.instr_mask = 0xef000000,
|
||||
.instr_val = 0xef000000,
|
||||
.cpsr_mask = MODE_MASK | PSR_T_BIT,
|
||||
.cpsr_val = SVC_MODE | PSR_T_BIT,
|
||||
.fn = vfp_kmode_exception,
|
||||
}, {
|
||||
.instr_mask = 0xff100000,
|
||||
.instr_val = 0xf9000000,
|
||||
.cpsr_mask = MODE_MASK | PSR_T_BIT,
|
||||
.cpsr_val = SVC_MODE | PSR_T_BIT,
|
||||
.fn = vfp_kmode_exception,
|
||||
}, {
|
||||
.instr_mask = 0x0c000e00,
|
||||
.instr_val = 0x0c000a00,
|
||||
.cpsr_mask = MODE_MASK,
|
||||
.cpsr_val = SVC_MODE,
|
||||
.fn = vfp_kmode_exception,
|
||||
}};
|
||||
|
||||
static int __init vfp_kmode_exception_hook_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(vfp_kmode_exception_hook); i++)
|
||||
register_undef_hook(&vfp_kmode_exception_hook[i]);
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(vfp_kmode_exception_hook_init);
|
||||
|
||||
/*
|
||||
* Kernel-side NEON support functions
|
||||
|
|
@ -708,6 +752,21 @@ EXPORT_SYMBOL(kernel_neon_end);
|
|||
|
||||
#endif /* CONFIG_KERNEL_MODE_NEON */
|
||||
|
||||
static int __init vfp_detect(struct pt_regs *regs, unsigned int instr)
|
||||
{
|
||||
VFP_arch = UINT_MAX; /* mark as not present */
|
||||
regs->ARM_pc += 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct undef_hook vfp_detect_hook __initdata = {
|
||||
.instr_mask = 0x0c000e00,
|
||||
.instr_val = 0x0c000a00,
|
||||
.cpsr_mask = MODE_MASK,
|
||||
.cpsr_val = SVC_MODE,
|
||||
.fn = vfp_detect,
|
||||
};
|
||||
|
||||
/*
|
||||
* VFP support code initialisation.
|
||||
*/
|
||||
|
|
@ -728,10 +787,11 @@ static int __init vfp_init(void)
|
|||
* The handler is already setup to just log calls, so
|
||||
* we just need to read the VFPSID register.
|
||||
*/
|
||||
vfp_vector = vfp_testing_entry;
|
||||
register_undef_hook(&vfp_detect_hook);
|
||||
barrier();
|
||||
vfpsid = fmrx(FPSID);
|
||||
barrier();
|
||||
unregister_undef_hook(&vfp_detect_hook);
|
||||
vfp_vector = vfp_null_entry;
|
||||
|
||||
pr_info("VFP support v0.3: ");
|
||||
|
|
|
|||
|
|
@ -340,7 +340,7 @@
|
|||
eee-broken-1000t;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -413,7 +413,7 @@
|
|||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -264,7 +264,7 @@
|
|||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@
|
|||
|
||||
/* External PHY reset is shared with internal PHY Led signal */
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
@ -341,7 +341,7 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "winbond,w25q16", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <3000000>;
|
||||
spi-max-frequency = <104000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@
|
|||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@
|
|||
|
||||
/* External PHY reset is shared with internal PHY Led signal */
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@
|
|||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@
|
|||
opp-microvolt = <790000>;
|
||||
};
|
||||
|
||||
opp-1512000000 {
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -79,8 +79,10 @@
|
|||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0xC4000003>;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
|
|
@ -481,13 +483,6 @@
|
|||
pmu_system_controller: system-controller@105c0000 {
|
||||
compatible = "samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x105c0000 0x5000>;
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@10590000 {
|
||||
|
|
@ -687,3 +682,4 @@
|
|||
};
|
||||
|
||||
#include "exynos7-pinctrl.dtsi"
|
||||
#include "arm/exynos-syscon-restart.dtsi"
|
||||
|
|
|
|||
|
|
@ -155,20 +155,10 @@
|
|||
};
|
||||
|
||||
partition@210000 {
|
||||
reg = <0x210000 0x0f0000>;
|
||||
reg = <0x210000 0x1d0000>;
|
||||
label = "bootloader";
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
reg = <0x300000 0x040000>;
|
||||
label = "DP firmware";
|
||||
};
|
||||
|
||||
partition@340000 {
|
||||
reg = <0x340000 0x0a0000>;
|
||||
label = "trusted firmware";
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
reg = <0x3e0000 0x020000>;
|
||||
label = "bootloader environment";
|
||||
|
|
|
|||
|
|
@ -309,7 +309,7 @@
|
|||
<0x0 0x20000000 0x0 0x10000000>;
|
||||
reg-names = "fspi_base", "fspi_mmap";
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clocks = <&clockgen 2 0>, <&clockgen 2 0>;
|
||||
clock-names = "fspi_en", "fspi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -934,7 +934,7 @@
|
|||
ethernet@0,4 {
|
||||
compatible = "fsl,enetc-ptp";
|
||||
reg = <0x000400 0 0 0 0>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clocks = <&clockgen 2 3>;
|
||||
little-endian;
|
||||
fsl,extts-fifo;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy = <&phy1>;
|
||||
phy-handle = <&phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,10 +15,6 @@
|
|||
"marvell,armada-ap806";
|
||||
};
|
||||
|
||||
&smmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
iommu-map =
|
||||
<0x0 &smmu 0x480 0x20>,
|
||||
|
|
|
|||
|
|
@ -15,10 +15,6 @@
|
|||
"marvell,armada-ap806";
|
||||
};
|
||||
|
||||
&smmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
iommu-map =
|
||||
<0x0 &smmu 0x480 0x20>,
|
||||
|
|
|
|||
|
|
@ -363,7 +363,7 @@
|
|||
compatible = "mediatek,mt8183-gce";
|
||||
reg = <0 0x10238000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
|
||||
#mbox-cells = <3>;
|
||||
#mbox-cells = <2>;
|
||||
clocks = <&infracfg CLK_INFRA_GCE>;
|
||||
clock-names = "gce";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -378,7 +378,7 @@
|
|||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
|
|
@ -390,7 +390,7 @@
|
|||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -156,8 +156,8 @@
|
|||
no-map;
|
||||
};
|
||||
|
||||
tz: tz@48500000 {
|
||||
reg = <0x0 0x48500000 0x0 0x00200000>;
|
||||
tz: memory@4a600000 {
|
||||
reg = <0x0 0x4a600000 0x0 0x00400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
|
|
@ -167,7 +167,7 @@
|
|||
};
|
||||
|
||||
q6_region: memory@4ab00000 {
|
||||
reg = <0x0 0x4ab00000 0x0 0x02800000>;
|
||||
reg = <0x0 0x4ab00000 0x0 0x05500000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -78,6 +78,9 @@
|
|||
sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&muic_i2c_default>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -314,6 +317,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
muic_i2c_default: muic-i2c-default {
|
||||
pins = "gpio105", "gpio106";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
muic_int_default: muic-int-default {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -1394,7 +1394,8 @@
|
|||
ipa: ipa@1e40000 {
|
||||
compatible = "qcom,sc7180-ipa";
|
||||
|
||||
iommus = <&apps_smmu 0x440 0x3>;
|
||||
iommus = <&apps_smmu 0x440 0x0>,
|
||||
<&apps_smmu 0x442 0x0>;
|
||||
reg = <0 0x1e40000 0 0x7000>,
|
||||
<0 0x1e47000 0 0x2000>,
|
||||
<0 0x1e04000 0 0x2c000>;
|
||||
|
|
@ -2811,7 +2812,7 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
|
|
|
|||
|
|
@ -2141,7 +2141,8 @@
|
|||
ipa: ipa@1e40000 {
|
||||
compatible = "qcom,sdm845-ipa";
|
||||
|
||||
iommus = <&apps_smmu 0x720 0x3>;
|
||||
iommus = <&apps_smmu 0x720 0x0>,
|
||||
<&apps_smmu 0x722 0x0>;
|
||||
reg = <0 0x1e40000 0 0x7000>,
|
||||
<0 0x1e47000 0 0x2000>,
|
||||
<0 0x1e04000 0 0x2c000>;
|
||||
|
|
|
|||
|
|
@ -264,23 +264,28 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@15 {
|
||||
tsel: hid@15 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x15>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_hid_active>;
|
||||
};
|
||||
|
||||
hid@2c {
|
||||
tsc2: hid@2c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x2c>;
|
||||
hid-descr-addr = <0x20>;
|
||||
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_hid_active>;
|
||||
pinctrl-0 = <&i2c3_hid_active>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -288,15 +293,15 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@10 {
|
||||
tsc1: hid@10 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x10>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_hid_active>;
|
||||
pinctrl-0 = <&i2c5_hid_active>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -304,7 +309,7 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@5c {
|
||||
ecsh: hid@5c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x5c>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
|
@ -312,7 +317,7 @@
|
|||
interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c12_hid_active>;
|
||||
pinctrl-0 = <&i2c11_hid_active>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -426,8 +431,8 @@
|
|||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
i2c2_hid_active: i2c2-hid-active {
|
||||
pins = <37>;
|
||||
i2c3_hid_active: i2c2-hid-active {
|
||||
pins = "gpio37";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
@ -435,8 +440,8 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
i2c6_hid_active: i2c6-hid-active {
|
||||
pins = <125>;
|
||||
i2c5_hid_active: i2c5-hid-active {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
@ -444,8 +449,8 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
i2c12_hid_active: i2c12-hid-active {
|
||||
pins = <92>;
|
||||
i2c11_hid_active: i2c11-hid-active {
|
||||
pins = "gpio92";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
@ -454,7 +459,7 @@
|
|||
};
|
||||
|
||||
wcd_intr_default: wcd_intr_default {
|
||||
pins = <54>;
|
||||
pins = "gpio54";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SM8250 MTP";
|
||||
compatible = "qcom,sm8250-mtp";
|
||||
compatible = "qcom,sm8250-mtp", "qcom,sm8250";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart12;
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@
|
|||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
|||
|
|
@ -334,6 +334,7 @@
|
|||
};
|
||||
|
||||
&usb20_otg {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1237,8 +1237,8 @@
|
|||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
|
||||
<1 RK_PB0 1 &pcfg_pull_none>;
|
||||
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
|
||||
<1 RK_PB0 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
|
|
@ -1256,8 +1256,8 @@
|
|||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
|
||||
<3 RK_PA6 4 &pcfg_pull_none>;
|
||||
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
|
||||
<3 RK_PA6 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
|
|
@ -1275,15 +1275,15 @@
|
|||
|
||||
uart2-0 {
|
||||
uart2m0_xfer: uart2m0-xfer {
|
||||
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
|
||||
<1 RK_PA1 2 &pcfg_pull_none>;
|
||||
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
|
||||
<1 RK_PA1 2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2-1 {
|
||||
uart2m1_xfer: uart2m1-xfer {
|
||||
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
|
||||
<2 RK_PA1 1 &pcfg_pull_none>;
|
||||
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
|
||||
<2 RK_PA1 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -834,7 +834,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dss: dss@04a00000 {
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,am65x-dss";
|
||||
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
|
||||
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
|
||||
|
|
@ -867,6 +867,8 @@
|
|||
|
||||
status = "disabled";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
dss_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -1278,7 +1278,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dss: dss@04a00000 {
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,j721e-dss";
|
||||
reg =
|
||||
<0x00 0x04a00000 0x00 0x10000>, /* common_m */
|
||||
|
|
|
|||
|
|
@ -840,7 +840,6 @@ poly1305_blocks_neon:
|
|||
ldp d14,d15,[sp,#64]
|
||||
addp $ACC2,$ACC2,$ACC2
|
||||
ldr x30,[sp,#8]
|
||||
.inst 0xd50323bf // autiasp
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// lazy reduction, but without narrowing
|
||||
|
|
@ -882,6 +881,7 @@ poly1305_blocks_neon:
|
|||
str x4,[$ctx,#8] // set is_base2_26
|
||||
|
||||
ldr x29,[sp],#80
|
||||
.inst 0xd50323bf // autiasp
|
||||
ret
|
||||
.size poly1305_blocks_neon,.-poly1305_blocks_neon
|
||||
|
||||
|
|
|
|||
|
|
@ -779,7 +779,6 @@ poly1305_blocks_neon:
|
|||
ldp d14,d15,[sp,#64]
|
||||
addp v21.2d,v21.2d,v21.2d
|
||||
ldr x30,[sp,#8]
|
||||
.inst 0xd50323bf // autiasp
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// lazy reduction, but without narrowing
|
||||
|
|
@ -821,6 +820,7 @@ poly1305_blocks_neon:
|
|||
str x4,[x0,#8] // set is_base2_26
|
||||
|
||||
ldr x29,[sp],#80
|
||||
.inst 0xd50323bf // autiasp
|
||||
ret
|
||||
.size poly1305_blocks_neon,.-poly1305_blocks_neon
|
||||
|
||||
|
|
|
|||
|
|
@ -214,6 +214,7 @@ enum vcpu_sysreg {
|
|||
#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
|
||||
#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
|
||||
#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
|
||||
#define c2_TTBCR2 (c2_TTBCR + 1) /* Translation Table Base Control R. 2 */
|
||||
#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
|
||||
#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
|
||||
#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
|
||||
|
|
|
|||
|
|
@ -189,7 +189,8 @@ long get_mte_ctrl(struct task_struct *task)
|
|||
|
||||
switch (task->thread.sctlr_tcf0) {
|
||||
case SCTLR_EL1_TCF0_NONE:
|
||||
return PR_MTE_TCF_NONE;
|
||||
ret |= PR_MTE_TCF_NONE;
|
||||
break;
|
||||
case SCTLR_EL1_TCF0_SYNC:
|
||||
ret |= PR_MTE_TCF_SYNC;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1987,6 +1987,7 @@ static const struct sys_reg_desc cp15_regs[] = {
|
|||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
|
||||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
|
||||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
|
||||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
|
||||
{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
|
||||
{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
|
||||
{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
|
||||
|
|
|
|||
|
|
@ -536,7 +536,7 @@ virtual_memmap_init(u64 start, u64 end, void *arg)
|
|||
|
||||
if (map_start < map_end)
|
||||
memmap_init_zone((unsigned long)(map_end - map_start),
|
||||
args->nid, args->zone, page_to_pfn(map_start),
|
||||
args->nid, args->zone, page_to_pfn(map_start), page_to_pfn(map_end),
|
||||
MEMINIT_EARLY, NULL, MIGRATE_MOVABLE);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -546,7 +546,7 @@ memmap_init (unsigned long size, int nid, unsigned long zone,
|
|||
unsigned long start_pfn)
|
||||
{
|
||||
if (!vmem_map) {
|
||||
memmap_init_zone(size, nid, zone, start_pfn,
|
||||
memmap_init_zone(size, nid, zone, start_pfn, start_pfn + size,
|
||||
MEMINIT_EARLY, NULL, MIGRATE_MOVABLE);
|
||||
} else {
|
||||
struct page *start;
|
||||
|
|
|
|||
|
|
@ -777,16 +777,12 @@ static struct resource scc_b_rsrcs[] = {
|
|||
struct platform_device scc_a_pdev = {
|
||||
.name = "scc",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(scc_a_rsrcs),
|
||||
.resource = scc_a_rsrcs,
|
||||
};
|
||||
EXPORT_SYMBOL(scc_a_pdev);
|
||||
|
||||
struct platform_device scc_b_pdev = {
|
||||
.name = "scc",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(scc_b_rsrcs),
|
||||
.resource = scc_b_rsrcs,
|
||||
};
|
||||
EXPORT_SYMBOL(scc_b_pdev);
|
||||
|
||||
|
|
@ -813,10 +809,15 @@ static void __init mac_identify(void)
|
|||
|
||||
/* Set up serial port resources for the console initcall. */
|
||||
|
||||
scc_a_rsrcs[0].start = (resource_size_t) mac_bi_data.sccbase + 2;
|
||||
scc_a_rsrcs[0].end = scc_a_rsrcs[0].start;
|
||||
scc_b_rsrcs[0].start = (resource_size_t) mac_bi_data.sccbase;
|
||||
scc_b_rsrcs[0].end = scc_b_rsrcs[0].start;
|
||||
scc_a_rsrcs[0].start = (resource_size_t)mac_bi_data.sccbase + 2;
|
||||
scc_a_rsrcs[0].end = scc_a_rsrcs[0].start;
|
||||
scc_a_pdev.num_resources = ARRAY_SIZE(scc_a_rsrcs);
|
||||
scc_a_pdev.resource = scc_a_rsrcs;
|
||||
|
||||
scc_b_rsrcs[0].start = (resource_size_t)mac_bi_data.sccbase;
|
||||
scc_b_rsrcs[0].end = scc_b_rsrcs[0].start;
|
||||
scc_b_pdev.num_resources = ARRAY_SIZE(scc_b_rsrcs);
|
||||
scc_b_pdev.resource = scc_b_rsrcs;
|
||||
|
||||
switch (macintosh_config->scc_type) {
|
||||
case MAC_SCC_PSC:
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ config BCM47XX_BCMA
|
|||
select BCMA
|
||||
select BCMA_HOST_SOC
|
||||
select BCMA_DRIVER_MIPS
|
||||
select BCMA_DRIVER_PCI if PCI
|
||||
select BCMA_DRIVER_PCI_HOSTMODE if PCI
|
||||
select BCMA_DRIVER_GPIO
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -498,8 +498,8 @@ static void __init request_crashkernel(struct resource *res)
|
|||
|
||||
static void __init check_kernel_sections_mem(void)
|
||||
{
|
||||
phys_addr_t start = PFN_PHYS(PFN_DOWN(__pa_symbol(&_text)));
|
||||
phys_addr_t size = PFN_PHYS(PFN_UP(__pa_symbol(&_end))) - start;
|
||||
phys_addr_t start = __pa_symbol(&_text);
|
||||
phys_addr_t size = __pa_symbol(&_end) - start;
|
||||
|
||||
if (!memblock_is_region_memory(start, size)) {
|
||||
pr_info("Kernel sections are not in the memory maps\n");
|
||||
|
|
|
|||
|
|
@ -368,6 +368,8 @@ initrd-y := $(filter-out $(image-y), $(initrd-y))
|
|||
targets += $(image-y) $(initrd-y)
|
||||
targets += $(foreach x, dtbImage uImage cuImage simpleImage treeImage, \
|
||||
$(patsubst $(x).%, dts/%.dtb, $(filter $(x).%, $(image-y))))
|
||||
targets += $(foreach x, dtbImage uImage cuImage simpleImage treeImage, \
|
||||
$(patsubst $(x).%, dts/fsl/%.dtb, $(filter $(x).%, $(image-y))))
|
||||
|
||||
$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
|
||||
|
||||
|
|
|
|||
|
|
@ -216,15 +216,34 @@ static inline void arch___clear_bit_unlock(int nr, volatile unsigned long *addr)
|
|||
*/
|
||||
static inline int fls(unsigned int x)
|
||||
{
|
||||
return 32 - __builtin_clz(x);
|
||||
int lz;
|
||||
|
||||
if (__builtin_constant_p(x))
|
||||
return x ? 32 - __builtin_clz(x) : 0;
|
||||
asm("cntlzw %0,%1" : "=r" (lz) : "r" (x));
|
||||
return 32 - lz;
|
||||
}
|
||||
|
||||
#include <asm-generic/bitops/builtin-__fls.h>
|
||||
|
||||
/*
|
||||
* 64-bit can do this using one cntlzd (count leading zeroes doubleword)
|
||||
* instruction; for 32-bit we use the generic version, which does two
|
||||
* 32-bit fls calls.
|
||||
*/
|
||||
#ifdef CONFIG_PPC64
|
||||
static inline int fls64(__u64 x)
|
||||
{
|
||||
return 64 - __builtin_clzll(x);
|
||||
int lz;
|
||||
|
||||
if (__builtin_constant_p(x))
|
||||
return x ? 64 - __builtin_clzll(x) : 0;
|
||||
asm("cntlzd %0,%1" : "=r" (lz) : "r" (x));
|
||||
return 64 - lz;
|
||||
}
|
||||
#else
|
||||
#include <asm-generic/bitops/fls64.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned int __arch_hweight8(unsigned int w);
|
||||
|
|
|
|||
|
|
@ -94,6 +94,7 @@ typedef struct {
|
|||
} mm_context_t;
|
||||
|
||||
void update_bats(void);
|
||||
static inline void cleanup_cpu_mmu_context(void) { };
|
||||
|
||||
/* patch sites */
|
||||
extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
|
||||
|
|
|
|||
|
|
@ -524,9 +524,9 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|||
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
||||
flush_hash_entry(mm, ptep, addr);
|
||||
__asm__ __volatile__("\
|
||||
stw%U0%X0 %2,%0\n\
|
||||
stw%X0 %2,%0\n\
|
||||
eieio\n\
|
||||
stw%U0%X0 %L2,%1"
|
||||
stw%X1 %L2,%1"
|
||||
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
||||
: "r" (pte) : "memory");
|
||||
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ extern void cpm_reset(void);
|
|||
#define PROFF_SPI ((uint)0x0180)
|
||||
#define PROFF_SCC3 ((uint)0x0200)
|
||||
#define PROFF_SMC1 ((uint)0x0280)
|
||||
#define PROFF_DSP1 ((uint)0x02c0)
|
||||
#define PROFF_SCC4 ((uint)0x0300)
|
||||
#define PROFF_SMC2 ((uint)0x0380)
|
||||
|
||||
|
|
|
|||
|
|
@ -369,7 +369,7 @@ static inline void cpu_feature_keys_init(void) { }
|
|||
CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
||||
#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
|
||||
CPU_FTR_MAYBE_CAN_NAP)
|
||||
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
|
||||
CPU_FTR_MAYBE_CAN_NAP | \
|
||||
CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
|
||||
|
|
@ -409,7 +409,6 @@ static inline void cpu_feature_keys_init(void) { }
|
|||
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
||||
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
|
||||
CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
|
||||
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
||||
|
||||
/* 64-bit CPUs */
|
||||
#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
|
||||
|
|
@ -520,8 +519,6 @@ enum {
|
|||
CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
|
||||
CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
|
||||
CPU_FTRS_CLASSIC32 |
|
||||
#else
|
||||
CPU_FTRS_GENERIC_32 |
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
CPU_FTRS_8XX |
|
||||
|
|
@ -596,8 +593,6 @@ enum {
|
|||
CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
|
||||
CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
|
||||
CPU_FTRS_CLASSIC32 &
|
||||
#else
|
||||
CPU_FTRS_GENERIC_32 &
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
CPU_FTRS_8XX &
|
||||
|
|
|
|||
|
|
@ -192,9 +192,9 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|||
*/
|
||||
if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) {
|
||||
__asm__ __volatile__("\
|
||||
stw%U0%X0 %2,%0\n\
|
||||
stw%X0 %2,%0\n\
|
||||
eieio\n\
|
||||
stw%U0%X0 %L2,%1"
|
||||
stw%X1 %L2,%1"
|
||||
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
||||
: "r" (pte) : "memory");
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -173,6 +173,9 @@ KCOV_INSTRUMENT_cputable.o := n
|
|||
KCOV_INSTRUMENT_setup_64.o := n
|
||||
KCOV_INSTRUMENT_paca.o := n
|
||||
|
||||
CFLAGS_setup_64.o += -fno-stack-protector
|
||||
CFLAGS_paca.o += -fno-stack-protector
|
||||
|
||||
extra-$(CONFIG_PPC_FPU) += fpu.o
|
||||
extra-$(CONFIG_ALTIVEC) += vector.o
|
||||
extra-$(CONFIG_PPC64) += entry_64.o
|
||||
|
|
|
|||
|
|
@ -131,18 +131,28 @@
|
|||
#ifdef CONFIG_VMAP_STACK
|
||||
mfspr r11, SPRN_SRR0
|
||||
mtctr r11
|
||||
#endif
|
||||
andi. r11, r9, MSR_PR
|
||||
mr r11, r1
|
||||
lwz r1,TASK_STACK-THREAD(r12)
|
||||
beq- 99f
|
||||
addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
|
||||
li r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
|
||||
mtmsr r10
|
||||
isync
|
||||
tovirt(r12, r12)
|
||||
stw r11,GPR1(r1)
|
||||
stw r11,0(r1)
|
||||
mr r11, r1
|
||||
#else
|
||||
andi. r11, r9, MSR_PR
|
||||
lwz r11,TASK_STACK-THREAD(r12)
|
||||
beq- 99f
|
||||
addi r11, r11, THREAD_SIZE - INT_FRAME_SIZE
|
||||
#ifdef CONFIG_VMAP_STACK
|
||||
li r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
|
||||
mtmsr r10
|
||||
isync
|
||||
tophys(r11, r11)
|
||||
stw r1,GPR1(r11)
|
||||
stw r1,0(r11)
|
||||
tovirt(r1, r11) /* set new kernel sp */
|
||||
#endif
|
||||
tovirt_vmstack r12, r12
|
||||
tophys_novmstack r11, r11
|
||||
mflr r10
|
||||
stw r10, _LINK(r11)
|
||||
#ifdef CONFIG_VMAP_STACK
|
||||
|
|
@ -150,9 +160,6 @@
|
|||
#else
|
||||
mfspr r10,SPRN_SRR0
|
||||
#endif
|
||||
stw r1,GPR1(r11)
|
||||
stw r1,0(r11)
|
||||
tovirt_novmstack r1, r11 /* set new kernel sp */
|
||||
stw r10,_NIP(r11)
|
||||
mfcr r10
|
||||
rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */
|
||||
|
|
|
|||
|
|
@ -417,6 +417,10 @@ generic_secondary_common_init:
|
|||
/* From now on, r24 is expected to be logical cpuid */
|
||||
mr r24,r5
|
||||
|
||||
/* Create a temp kernel stack for use before relocation is on. */
|
||||
ld r1,PACAEMERGSP(r13)
|
||||
subi r1,r1,STACK_FRAME_OVERHEAD
|
||||
|
||||
/* See if we need to call a cpu state restore handler */
|
||||
LOAD_REG_ADDR(r23, cur_cpu_spec)
|
||||
ld r23,0(r23)
|
||||
|
|
@ -445,10 +449,6 @@ generic_secondary_common_init:
|
|||
sync /* order paca.run and cur_cpu_spec */
|
||||
isync /* In case code patching happened */
|
||||
|
||||
/* Create a temp kernel stack for use before relocation is on. */
|
||||
ld r1,PACAEMERGSP(r13)
|
||||
subi r1,r1,STACK_FRAME_OVERHEAD
|
||||
|
||||
b __secondary_start
|
||||
#endif /* SMP */
|
||||
|
||||
|
|
@ -990,7 +990,7 @@ start_here_common:
|
|||
bl start_kernel
|
||||
|
||||
/* Not reached */
|
||||
trap
|
||||
0: trap
|
||||
EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
|
||||
.previous
|
||||
|
||||
|
|
|
|||
|
|
@ -102,14 +102,6 @@ static inline notrace unsigned long get_irq_happened(void)
|
|||
return happened;
|
||||
}
|
||||
|
||||
static inline notrace int decrementer_check_overflow(void)
|
||||
{
|
||||
u64 now = get_tb();
|
||||
u64 *next_tb = this_cpu_ptr(&decrementers_next_tb);
|
||||
|
||||
return now >= *next_tb;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3E
|
||||
|
||||
/* This is called whenever we are re-enabling interrupts
|
||||
|
|
@ -142,35 +134,6 @@ notrace unsigned int __check_irq_replay(void)
|
|||
trace_hardirqs_on();
|
||||
trace_hardirqs_off();
|
||||
|
||||
/*
|
||||
* We are always hard disabled here, but PACA_IRQ_HARD_DIS may
|
||||
* not be set, which means interrupts have only just been hard
|
||||
* disabled as part of the local_irq_restore or interrupt return
|
||||
* code. In that case, skip the decrementr check becaus it's
|
||||
* expensive to read the TB.
|
||||
*
|
||||
* HARD_DIS then gets cleared here, but it's reconciled later.
|
||||
* Either local_irq_disable will replay the interrupt and that
|
||||
* will reconcile state like other hard interrupts. Or interrupt
|
||||
* retur will replay the interrupt and in that case it sets
|
||||
* PACA_IRQ_HARD_DIS by hand (see comments in entry_64.S).
|
||||
*/
|
||||
if (happened & PACA_IRQ_HARD_DIS) {
|
||||
local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
|
||||
|
||||
/*
|
||||
* We may have missed a decrementer interrupt if hard disabled.
|
||||
* Check the decrementer register in case we had a rollover
|
||||
* while hard disabled.
|
||||
*/
|
||||
if (!(happened & PACA_IRQ_DEC)) {
|
||||
if (decrementer_check_overflow()) {
|
||||
local_paca->irq_happened |= PACA_IRQ_DEC;
|
||||
happened |= PACA_IRQ_DEC;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (happened & PACA_IRQ_DEC) {
|
||||
local_paca->irq_happened &= ~PACA_IRQ_DEC;
|
||||
return 0x900;
|
||||
|
|
@ -186,6 +149,9 @@ notrace unsigned int __check_irq_replay(void)
|
|||
return 0x280;
|
||||
}
|
||||
|
||||
if (happened & PACA_IRQ_HARD_DIS)
|
||||
local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
|
||||
|
||||
/* There should be nothing left ! */
|
||||
BUG_ON(local_paca->irq_happened != 0);
|
||||
|
||||
|
|
@ -229,18 +195,6 @@ again:
|
|||
if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
|
||||
WARN_ON_ONCE(mfmsr() & MSR_EE);
|
||||
|
||||
if (happened & PACA_IRQ_HARD_DIS) {
|
||||
/*
|
||||
* We may have missed a decrementer interrupt if hard disabled.
|
||||
* Check the decrementer register in case we had a rollover
|
||||
* while hard disabled.
|
||||
*/
|
||||
if (!(happened & PACA_IRQ_DEC)) {
|
||||
if (decrementer_check_overflow())
|
||||
happened |= PACA_IRQ_DEC;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Force the delivery of pending soft-disabled interrupts on PS3.
|
||||
* Any HV call will have this side effect.
|
||||
|
|
@ -345,6 +299,7 @@ notrace void arch_local_irq_restore(unsigned long mask)
|
|||
if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
|
||||
WARN_ON_ONCE(!(mfmsr() & MSR_EE));
|
||||
__hard_irq_disable();
|
||||
local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
|
||||
} else {
|
||||
/*
|
||||
* We should already be hard disabled here. We had bugs
|
||||
|
|
|
|||
|
|
@ -208,7 +208,7 @@ static struct rtas_args * __init new_rtas_args(int cpu, unsigned long limit)
|
|||
struct paca_struct **paca_ptrs __read_mostly;
|
||||
EXPORT_SYMBOL(paca_ptrs);
|
||||
|
||||
void __init __nostackprotector initialise_paca(struct paca_struct *new_paca, int cpu)
|
||||
void __init initialise_paca(struct paca_struct *new_paca, int cpu)
|
||||
{
|
||||
#ifdef CONFIG_PPC_PSERIES
|
||||
new_paca->lppaca_ptr = NULL;
|
||||
|
|
@ -241,7 +241,7 @@ void __init __nostackprotector initialise_paca(struct paca_struct *new_paca, int
|
|||
}
|
||||
|
||||
/* Put the paca pointer into r13 and SPRG_PACA */
|
||||
void __nostackprotector setup_paca(struct paca_struct *new_paca)
|
||||
void setup_paca(struct paca_struct *new_paca)
|
||||
{
|
||||
/* Setup r13 */
|
||||
local_paca = new_paca;
|
||||
|
|
|
|||
|
|
@ -1030,7 +1030,7 @@ static struct rtas_filter rtas_filters[] __ro_after_init = {
|
|||
{ "ibm,display-message", -1, 0, -1, -1, -1 },
|
||||
{ "ibm,errinjct", -1, 2, -1, -1, -1, 1024 },
|
||||
{ "ibm,close-errinjct", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,open-errinct", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,open-errinjct", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,get-config-addr-info2", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,get-dynamic-sensor-state", -1, 1, -1, -1, -1 },
|
||||
{ "ibm,get-indices", -1, 2, 3, -1, -1 },
|
||||
|
|
|
|||
|
|
@ -919,8 +919,6 @@ void __init setup_arch(char **cmdline_p)
|
|||
|
||||
/* On BookE, setup per-core TLB data structures. */
|
||||
setup_tlb_core_data();
|
||||
|
||||
smp_release_cpus();
|
||||
#endif
|
||||
|
||||
/* Print various info about the machine that has been gathered so far. */
|
||||
|
|
@ -944,6 +942,8 @@ void __init setup_arch(char **cmdline_p)
|
|||
exc_lvl_early_init();
|
||||
emergency_stack_init();
|
||||
|
||||
smp_release_cpus();
|
||||
|
||||
initmem_init();
|
||||
|
||||
early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT);
|
||||
|
|
|
|||
|
|
@ -8,12 +8,6 @@
|
|||
#ifndef __ARCH_POWERPC_KERNEL_SETUP_H
|
||||
#define __ARCH_POWERPC_KERNEL_SETUP_H
|
||||
|
||||
#ifdef CONFIG_CC_IS_CLANG
|
||||
#define __nostackprotector
|
||||
#else
|
||||
#define __nostackprotector __attribute__((__optimize__("no-stack-protector")))
|
||||
#endif
|
||||
|
||||
void initialize_cache_info(void);
|
||||
void irqstack_early_init(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -283,7 +283,7 @@ void __init record_spr_defaults(void)
|
|||
* device-tree is not accessible via normal means at this point.
|
||||
*/
|
||||
|
||||
void __init __nostackprotector early_setup(unsigned long dt_ptr)
|
||||
void __init early_setup(unsigned long dt_ptr)
|
||||
{
|
||||
static __initdata struct paca_struct boot_paca;
|
||||
|
||||
|
|
|
|||
|
|
@ -919,7 +919,7 @@ static struct sched_domain_topology_level powerpc_topology[] = {
|
|||
{ NULL, },
|
||||
};
|
||||
|
||||
static int init_big_cores(void)
|
||||
static int __init init_big_cores(void)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
|
|
|
|||
|
|
@ -552,14 +552,11 @@ void timer_interrupt(struct pt_regs *regs)
|
|||
struct pt_regs *old_regs;
|
||||
u64 now;
|
||||
|
||||
/* Some implementations of hotplug will get timer interrupts while
|
||||
* offline, just ignore these and we also need to set
|
||||
* decrementers_next_tb as MAX to make sure __check_irq_replay
|
||||
* don't replay timer interrupt when return, otherwise we'll trap
|
||||
* here infinitely :(
|
||||
/*
|
||||
* Some implementations of hotplug will get timer interrupts while
|
||||
* offline, just ignore these.
|
||||
*/
|
||||
if (unlikely(!cpu_online(smp_processor_id()))) {
|
||||
*next_tb = ~(u64)0;
|
||||
set_dec(decrementer_max);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1346,6 +1346,9 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
|
|||
switch (opcode) {
|
||||
#ifdef __powerpc64__
|
||||
case 1:
|
||||
if (!cpu_has_feature(CPU_FTR_ARCH_31))
|
||||
return -1;
|
||||
|
||||
prefix_r = GET_PREFIX_R(word);
|
||||
ra = GET_PREFIX_RA(suffix);
|
||||
rd = (suffix >> 21) & 0x1f;
|
||||
|
|
@ -2733,6 +2736,9 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
|
|||
}
|
||||
break;
|
||||
case 1: /* Prefixed instructions */
|
||||
if (!cpu_has_feature(CPU_FTR_ARCH_31))
|
||||
return -1;
|
||||
|
||||
prefix_r = GET_PREFIX_R(word);
|
||||
ra = GET_PREFIX_RA(suffix);
|
||||
op->update_reg = ra;
|
||||
|
|
@ -2751,6 +2757,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
|
|||
case 41: /* plwa */
|
||||
op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
|
||||
break;
|
||||
#ifdef CONFIG_VSX
|
||||
case 42: /* plxsd */
|
||||
op->reg = rd + 32;
|
||||
op->type = MKOP(LOAD_VSX, PREFIXED, 8);
|
||||
|
|
@ -2791,13 +2798,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
|
|||
op->element_size = 16;
|
||||
op->vsx_flags = VSX_CHECK_VEC;
|
||||
break;
|
||||
#endif /* CONFIG_VSX */
|
||||
case 56: /* plq */
|
||||
op->type = MKOP(LOAD, PREFIXED, 16);
|
||||
break;
|
||||
case 57: /* pld */
|
||||
op->type = MKOP(LOAD, PREFIXED, 8);
|
||||
break;
|
||||
case 60: /* stq */
|
||||
case 60: /* pstq */
|
||||
op->type = MKOP(STORE, PREFIXED, 16);
|
||||
break;
|
||||
case 61: /* pstd */
|
||||
|
|
|
|||
|
|
@ -303,7 +303,6 @@ static inline void cmo_account_page_fault(void)
|
|||
static inline void cmo_account_page_fault(void) { }
|
||||
#endif /* CONFIG_PPC_SMLPAR */
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3S
|
||||
static void sanity_check_fault(bool is_write, bool is_user,
|
||||
unsigned long error_code, unsigned long address)
|
||||
{
|
||||
|
|
@ -320,6 +319,9 @@ static void sanity_check_fault(bool is_write, bool is_user,
|
|||
return;
|
||||
}
|
||||
|
||||
if (!IS_ENABLED(CONFIG_PPC_BOOK3S))
|
||||
return;
|
||||
|
||||
/*
|
||||
* For hash translation mode, we should never get a
|
||||
* PROTFAULT. Any update to pte to reduce access will result in us
|
||||
|
|
@ -354,10 +356,6 @@ static void sanity_check_fault(bool is_write, bool is_user,
|
|||
|
||||
WARN_ON_ONCE(error_code & DSISR_PROTFAULT);
|
||||
}
|
||||
#else
|
||||
static void sanity_check_fault(bool is_write, bool is_user,
|
||||
unsigned long error_code, unsigned long address) { }
|
||||
#endif /* CONFIG_PPC_BOOK3S */
|
||||
|
||||
/*
|
||||
* Define the correct "is_write" bit in error_code based
|
||||
|
|
|
|||
|
|
@ -532,7 +532,7 @@ void __flush_dcache_icache(void *p)
|
|||
* space occurs, before returning to user space.
|
||||
*/
|
||||
|
||||
if (cpu_has_feature(MMU_FTR_TYPE_44x))
|
||||
if (mmu_has_feature(MMU_FTR_TYPE_44x))
|
||||
return;
|
||||
|
||||
invalidate_icache_range(addr, addr + PAGE_SIZE);
|
||||
|
|
|
|||
|
|
@ -137,6 +137,9 @@ static void pmao_restore_workaround(bool ebb) { }
|
|||
|
||||
bool is_sier_available(void)
|
||||
{
|
||||
if (!ppmu)
|
||||
return false;
|
||||
|
||||
if (ppmu->flags & PPMU_HAS_SIER)
|
||||
return true;
|
||||
|
||||
|
|
@ -2121,6 +2124,16 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
|
|||
local64_set(&event->hw.period_left, left);
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
/*
|
||||
* Due to hardware limitation, sometimes SIAR could sample a kernel
|
||||
* address even when freeze on supervisor state (kernel) is set in
|
||||
* MMCR2. Check attr.exclude_kernel and address to drop the sample in
|
||||
* these cases.
|
||||
*/
|
||||
if (event->attr.exclude_kernel && record)
|
||||
if (is_kernel_addr(mfspr(SPRN_SIAR)))
|
||||
record = 0;
|
||||
|
||||
/*
|
||||
* Finally record data if requested.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight)
|
|||
u64 sier = mfspr(SPRN_SIER);
|
||||
u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
||||
mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
|
||||
|
||||
if (val == 0 || val == 7)
|
||||
*weight = 0;
|
||||
else
|
||||
|
|
@ -311,9 +314,11 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
|
|||
}
|
||||
|
||||
if (unit >= 6 && unit <= 9) {
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
|
||||
mask |= CNST_L2L3_GROUP_MASK;
|
||||
value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
||||
if (unit == 6) {
|
||||
mask |= CNST_L2L3_GROUP_MASK;
|
||||
value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
|
||||
}
|
||||
} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
||||
mask |= CNST_CACHE_GROUP_MASK;
|
||||
value |= CNST_CACHE_GROUP_VAL(event & 0xff);
|
||||
|
|
@ -339,12 +344,22 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
|
|||
value |= CNST_L1_QUAL_VAL(cache);
|
||||
}
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
||||
mask |= CNST_RADIX_SCOPE_GROUP_MASK;
|
||||
value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
|
||||
}
|
||||
|
||||
if (is_event_marked(event)) {
|
||||
mask |= CNST_SAMPLE_MASK;
|
||||
value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
|
||||
}
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
||||
if (event_is_threshold(event)) {
|
||||
mask |= CNST_THRESH_CTL_SEL_MASK;
|
||||
value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
|
||||
}
|
||||
} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
||||
if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
|
||||
mask |= CNST_THRESH_MASK;
|
||||
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
|
||||
|
|
@ -456,6 +471,13 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
|
|||
}
|
||||
}
|
||||
|
||||
/* Set RADIX_SCOPE_QUAL bit */
|
||||
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
||||
val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
|
||||
p10_EVENT_RADIX_SCOPE_QUAL_MASK;
|
||||
mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
|
||||
}
|
||||
|
||||
if (is_event_marked(event[i])) {
|
||||
mmcra |= MMCRA_SAMPLE_ENABLE;
|
||||
|
||||
|
|
|
|||
|
|
@ -101,6 +101,9 @@
|
|||
#define p10_EVENT_CACHE_SEL_MASK 0x3ull
|
||||
#define p10_EVENT_MMCR3_MASK 0x7fffull
|
||||
#define p10_EVENT_MMCR3_SHIFT 45
|
||||
#define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT 9
|
||||
#define p10_EVENT_RADIX_SCOPE_QUAL_MASK 0x1
|
||||
#define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT 45
|
||||
|
||||
#define p10_EVENT_VALID_MASK \
|
||||
((p10_SDAR_MODE_MASK << p10_SDAR_MODE_SHIFT | \
|
||||
|
|
@ -112,6 +115,7 @@
|
|||
(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \
|
||||
(p10_EVENT_MMCR3_MASK << p10_EVENT_MMCR3_SHIFT) | \
|
||||
(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
|
||||
(p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) | \
|
||||
EVENT_LINUX_MASK | \
|
||||
EVENT_PSEL_MASK))
|
||||
/*
|
||||
|
|
@ -125,9 +129,9 @@
|
|||
*
|
||||
* 28 24 20 16 12 8 4 0
|
||||
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
|
||||
* [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
|
||||
* | | | |
|
||||
* BHRB IFM -* | | | Count of events for each PMC.
|
||||
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
|
||||
* | | | | |
|
||||
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
|
||||
* EBB -* | | p1, p2, p3, p4, p5, p6.
|
||||
* L1 I/D qualifier -* |
|
||||
* nc - number of counters -*
|
||||
|
|
@ -145,6 +149,9 @@
|
|||
#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
|
||||
#define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
|
||||
|
||||
#define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32)
|
||||
#define CNST_THRESH_CTL_SEL_MASK CNST_THRESH_CTL_SEL_VAL(0x7ff)
|
||||
|
||||
#define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
|
||||
#define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
|
||||
|
||||
|
|
@ -165,6 +172,9 @@
|
|||
#define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55)
|
||||
#define CNST_L2L3_GROUP_MASK CNST_L2L3_GROUP_VAL(0x1f)
|
||||
|
||||
#define CNST_RADIX_SCOPE_GROUP_VAL(v) (((v) & 0x1ull) << 21)
|
||||
#define CNST_RADIX_SCOPE_GROUP_MASK CNST_RADIX_SCOPE_GROUP_VAL(1)
|
||||
|
||||
/*
|
||||
* For NC we are counting up to 4 events. This requires three bits, and we need
|
||||
* the fifth event to overflow and set the 4th bit. To achieve that we bias the
|
||||
|
|
@ -221,6 +231,10 @@
|
|||
#define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
|
||||
MMCRA_THR_CTR_EXP_MASK)
|
||||
|
||||
#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul
|
||||
#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
|
||||
P10_MMCRA_THR_CTR_MANT_MASK)
|
||||
|
||||
/* MMCRA Threshold Compare bit constant for power9 */
|
||||
#define p9_MMCRA_THR_CMP_SHIFT 45
|
||||
|
||||
|
|
|
|||
|
|
@ -23,10 +23,10 @@
|
|||
*
|
||||
* 28 24 20 16 12 8 4 0
|
||||
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
|
||||
* [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] m [ pmcxsel ]
|
||||
* | | | | | |
|
||||
* | | | | | *- mark
|
||||
* | | | *- L1/L2/L3 cache_sel |
|
||||
* [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ]
|
||||
* | | | | | | |
|
||||
* | | | | | | *- mark
|
||||
* | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
|
||||
* | | sdar_mode |
|
||||
* | *- sampling mode for marked events *- combine
|
||||
* |
|
||||
|
|
@ -59,6 +59,7 @@
|
|||
*
|
||||
* MMCR1[16] = cache_sel[0]
|
||||
* MMCR1[17] = cache_sel[1]
|
||||
* MMCR1[18] = radix_scope_qual
|
||||
*
|
||||
* if mark:
|
||||
* MMCRA[63] = 1 (SAMPLE_ENABLE)
|
||||
|
|
@ -175,6 +176,7 @@ PMU_FORMAT_ATTR(src_sel, "config:45-46");
|
|||
PMU_FORMAT_ATTR(invert_bit, "config:47");
|
||||
PMU_FORMAT_ATTR(src_mask, "config:48-53");
|
||||
PMU_FORMAT_ATTR(src_match, "config:54-59");
|
||||
PMU_FORMAT_ATTR(radix_scope, "config:9");
|
||||
|
||||
static struct attribute *power10_pmu_format_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
|
|
@ -194,6 +196,7 @@ static struct attribute *power10_pmu_format_attr[] = {
|
|||
&format_attr_invert_bit.attr,
|
||||
&format_attr_src_mask.attr,
|
||||
&format_attr_src_match.attr,
|
||||
&format_attr_radix_scope.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -360,6 +360,17 @@ void __init cpm_load_patch(cpm8xx_t *cp)
|
|||
if (IS_ENABLED(CONFIG_SMC_UCODE_PATCH)) {
|
||||
smc_uart_t *smp;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PPC_EARLY_DEBUG_CPM)) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(*smp); i += 4) {
|
||||
u32 __iomem *src = (u32 __iomem *)&cp->cp_dparam[PROFF_SMC1 + i];
|
||||
u32 __iomem *dst = (u32 __iomem *)&cp->cp_dparam[PROFF_DSP1 + i];
|
||||
|
||||
out_be32(dst, in_be32(src));
|
||||
}
|
||||
}
|
||||
|
||||
smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC1];
|
||||
out_be16(&smp->smc_rpbase, 0x1ec0);
|
||||
smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC2];
|
||||
|
|
|
|||
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Add table
Reference in a new issue