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This pull request contains the following notable changes:
- introduce support to the SPI 1-2-2 and 1-4-4 protocols. - introduce support to the Double Data Rate (DDR) mode. - introduce support to the Octo SPI protocols. - add support to new memory parts for Spansion, Macronix and Winbond. - add fixes for the Aspeed, STM32 and Cadence QSPI controler drivers. - clean up the st_spi_fsm driver. -----BEGIN PGP SIGNATURE----- iQI4BAABCAAiBQJZV6mQGxxjeXJpbGxlLnBpdGNoZW5Ad2VkZXY0dS5mcgAKCRDn 4OgLHRpJcnqMD/9BVRi6qdKeGU3u6d1osgXSCwnFQ8K4vKzgjht+oNmd3vUTDjbd cbqtSQUGeXsBRwA6JJXQlRJOB9+hsaBrBjfeG/LuDFgFvGWJ2vevgd1v0FftSiqE jA+Vg6CuIZJvNjdl1E1UsXJ8hcP4xcQADzd8bhjqhQsZOLYfGqG6/nPSpiUI4JWU 3KsNhJ6HoN/PWNBRNjanGm6d6HRyu0C/GtDT0N9tGKqupas/xkH/cPCHyCkF8nBH Tp/IPTw6KmyVBmtMzcTzlR/SVUld3LEZfFQk5FpO8InwUArx4lyKCDp4EIWhhBEC QSTL7EmqUuAZTq+JhSyniVjUw9GA54hKcHBaH3NC5uaV0d3cePaWt8rtxKGXVH13 9SY5U4IBlAzEDC3gpD777Lu4Qhj3YelLetRPUtumnc6i7t0qYFIWgO/3yFxYSWdH pFYmIooqG0DQzpwmFTFFiGep4fftxNyMA5DhlzZWfU3OKbvPJ2035QSz5nu/iysZ hhYV205FTsE0D33eBFoVkijKn3mEosTlVyvVofkaFbz6dqIY3t8vv8Wx07aEpTqF WcQ3iCw7x9nO/dBQ/Q25fTvssOlcNzrB4v+SlGfxcFH3gHprwx7PEaT1YHf9qtaF 4hP4UludGHCUZgOZGxfk0r5aLNmXD8aNUhEGkt44pdrItDDRfWQTUc0fcQ== =ZHnm -----END PGP SIGNATURE----- Merge tag 'spi-nor/for-4.13' into MTD From Cyrille: """ This pull request contains the following notable changes: - introduce support to the SPI 1-2-2 and 1-4-4 protocols. - introduce support to the Double Data Rate (DDR) mode. - introduce support to the Octo SPI protocols. - add support to new memory parts for Spansion, Macronix and Winbond. - add fixes for the Aspeed, STM32 and Cadence QSPI controler drivers. - clean up the st_spi_fsm driver. """
This commit is contained in:
Brian Norris
commit
8b9ef8f955
15 changed files with 937 additions and 239 deletions
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@ -73,6 +73,15 @@
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#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
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#define SPINOR_OP_READ_1_1_1_DTR 0x0d
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#define SPINOR_OP_READ_1_2_2_DTR 0xbd
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#define SPINOR_OP_READ_1_4_4_DTR 0xed
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#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
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#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
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#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
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/* Used for SST flashes only. */
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#define SPINOR_OP_BP 0x02 /* Byte program */
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#define SPINOR_OP_WRDI 0x04 /* Write disable */
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@ -119,13 +128,81 @@
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/* Configuration Register bits. */
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#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
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enum read_mode {
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SPI_NOR_NORMAL = 0,
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SPI_NOR_FAST,
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SPI_NOR_DUAL,
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SPI_NOR_QUAD,
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/* Supported SPI protocols */
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#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
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#define SNOR_PROTO_INST_SHIFT 16
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#define SNOR_PROTO_INST(_nbits) \
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((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
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SNOR_PROTO_INST_MASK)
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#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
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#define SNOR_PROTO_ADDR_SHIFT 8
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#define SNOR_PROTO_ADDR(_nbits) \
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((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
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SNOR_PROTO_ADDR_MASK)
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#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
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#define SNOR_PROTO_DATA_SHIFT 0
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#define SNOR_PROTO_DATA(_nbits) \
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((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
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SNOR_PROTO_DATA_MASK)
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#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
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#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
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(SNOR_PROTO_INST(_inst_nbits) | \
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SNOR_PROTO_ADDR(_addr_nbits) | \
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SNOR_PROTO_DATA(_data_nbits))
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#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
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(SNOR_PROTO_IS_DTR | \
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SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
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enum spi_nor_protocol {
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SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
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SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
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SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
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SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
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SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
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SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
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SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
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SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
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SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
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SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
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SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
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SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
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SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
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SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
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};
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static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
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{
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return !!(proto & SNOR_PROTO_IS_DTR);
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}
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static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
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{
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return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
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SNOR_PROTO_INST_SHIFT;
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}
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static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
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{
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return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
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SNOR_PROTO_ADDR_SHIFT;
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}
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static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
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{
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return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
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SNOR_PROTO_DATA_SHIFT;
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}
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static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
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{
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return spi_nor_get_protocol_data_nbits(proto);
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}
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#define SPI_NOR_MAX_CMD_SIZE 8
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enum spi_nor_ops {
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SPI_NOR_OPS_READ = 0,
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@ -154,9 +231,11 @@ enum spi_nor_option_flags {
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* @read_opcode: the read opcode
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* @read_dummy: the dummy needed by the read operation
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* @program_opcode: the program opcode
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* @flash_read: the mode of the read
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* @sst_write_second: used by the SST write operation
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* @flags: flag options for the current SPI-NOR (SNOR_F_*)
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* @read_proto: the SPI protocol for read operations
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* @write_proto: the SPI protocol for write operations
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* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
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* @cmd_buf: used by the write_reg
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* @prepare: [OPTIONAL] do some preparations for the
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* read/write/erase/lock/unlock operations
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@ -185,7 +264,9 @@ struct spi_nor {
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u8 read_opcode;
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u8 read_dummy;
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u8 program_opcode;
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enum read_mode flash_read;
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enum spi_nor_protocol read_proto;
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enum spi_nor_protocol write_proto;
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enum spi_nor_protocol reg_proto;
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bool sst_write_second;
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u32 flags;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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@ -219,11 +300,72 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
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return mtd_get_of_node(&nor->mtd);
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}
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/**
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* struct spi_nor_hwcaps - Structure for describing the hardware capabilies
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* supported by the SPI controller (bus master).
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* @mask: the bitmask listing all the supported hw capabilies
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*/
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struct spi_nor_hwcaps {
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u32 mask;
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};
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/*
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*(Fast) Read capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* As a matter of performances, it is relevant to use Octo SPI protocols first,
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* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
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* (Slow) Read.
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*/
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#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
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#define SNOR_HWCAPS_READ BIT(0)
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#define SNOR_HWCAPS_READ_FAST BIT(1)
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#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
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#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
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#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
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#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
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#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
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#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
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#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
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#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
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#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
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#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
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#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
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#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
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#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
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#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
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#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
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#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
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/*
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* Page Program capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
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* legacy SPI 1-1-1 protocol.
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* Note that Dual Page Programs are not supported because there is no existing
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* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
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* implements such commands.
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*/
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#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
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#define SNOR_HWCAPS_PP BIT(16)
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#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
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#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
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#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
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#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
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#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
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#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
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#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
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#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
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/**
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* spi_nor_scan() - scan the SPI NOR
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* @nor: the spi_nor structure
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* @name: the chip type name
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* @mode: the read mode supported by the driver
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* @hwcaps: the hardware capabilities supported by the controller driver
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*
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* The drivers can use this fuction to scan the SPI NOR.
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* In the scanning, it will try to get all the necessary information to
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@ -233,6 +375,7 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
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*
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* Return: 0 for success, others for failure.
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*/
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int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);
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int spi_nor_scan(struct spi_nor *nor, const char *name,
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const struct spi_nor_hwcaps *hwcaps);
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#endif
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