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platform/x86/amd: pmc: Move idlemask check into amd_pmc_idlemask_read

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The version check requirement for idle mask support actually only
applies to RN/CZN/BRC platforms.

So far no issues have happened because the PMFW version string is
bigger on other supported systems.  This can be reset for any new platform
so move the check to only RN/CZN/BRC case.

Fixes: f6045de1f5 ("platform/x86: amd-pmc: Export Idlemask values based on the APU")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230409185348.556161-5-Shyam-sundar.S-k@amd.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Mario Limonciello 2023-04-10 00:23:44 +05:30 • committed by Hans de Goede
parent 7abc3618b6
commit 9217bd1d76
1 changed files with 33 additions and 41 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

74
drivers/platform/x86/amd/pmc.c
View file

@ -342,33 +342,6 @@ static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
return 0; return 0;
} }
static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
struct seq_file *s)
{
u32 val;
switch (pdev->cpu_id) {
case AMD_CPU_ID_CZN:
val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
break;
case AMD_CPU_ID_YC:
case AMD_CPU_ID_CB:
case AMD_CPU_ID_PS:
val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
break;
default:
return -EINVAL;
}
if (dev)
dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
if (s)
seq_printf(s, "SMU idlemask : 0x%x\n", val);
return 0;
}
static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
{ {
if (!pdev->smu_virt_addr) { if (!pdev->smu_virt_addr) {
@ -543,28 +516,47 @@ static int s0ix_stats_show(struct seq_file *s, void *unused)
} }
DEFINE_SHOW_ATTRIBUTE(s0ix_stats); DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
struct seq_file *s)
{ {
struct amd_pmc_dev *dev = s->private; u32 val;
int rc; int rc;
/* we haven't yet read SMU version */ switch (pdev->cpu_id) {
if (!dev->major) { case AMD_CPU_ID_CZN:
rc = amd_pmc_get_smu_version(dev); /* we haven't yet read SMU version */
if (rc) if (!pdev->major) {
return rc; rc = amd_pmc_get_smu_version(pdev);
if (rc)
return rc;
}
if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
else
return -EINVAL;
break;
case AMD_CPU_ID_YC:
case AMD_CPU_ID_CB:
case AMD_CPU_ID_PS:
val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
break;
default:
return -EINVAL;
} }
if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) { if (dev)
rc = amd_pmc_idlemask_read(dev, NULL, s); dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
if (rc)
return rc; if (s)
} else { seq_printf(s, "SMU idlemask : 0x%x\n", val);
seq_puts(s, "Unsupported SMU version for Idlemask\n");
}
return 0; return 0;
} }
static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
{
return amd_pmc_idlemask_read(s->private, NULL, s);
}
DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)