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[MIPS] PMC MSP71xx mips common

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Patch to add mips common support for the PMC-Sierra MSP71xx devices.

Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Marc St-Jean 2007-06-14 15:55:31 -06:00 • committed by Ralf Baechle
parent 35832e26f9
commit 9267a30d1d
10 changed files with 179 additions and 2 deletions
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33
include/asm-mips/mipsregs.h
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@ -15,6 +15,7 @@
#include <linux/linkage.h>
#include <asm/hazards.h>
#include <asm/war.h>
/*
* The following macros are especially useful for __asm__
@ -537,6 +538,9 @@
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
@ -1298,10 +1302,39 @@ static inline void tlb_probe(void)
static inline void tlb_read(void)
{
#if MIPS34K_MISSED_ITLB_WAR
int res = 0;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set noat \n"
" .set mips32r2 \n"
" .word 0x41610001 # dvpe $1 \n"
" move %0, $1 \n"
" ehb \n"
" .set pop \n"
: "=r" (res));
instruction_hazard();
#endif
__asm__ __volatile__(
".set noreorder\n\t"
"tlbr\n\t"
".set reorder");
#if MIPS34K_MISSED_ITLB_WAR
if ((res & _ULCAST_(1)))
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set noat \n"
" .set mips32r2 \n"
" .word 0x41600021 # evpe \n"
" ehb \n"
" .set pop \n");
#endif
}
static inline void tlb_write_indexed(void)