GitHub-Mirror/Star64_linux
2
0
Fork 0
mirror of https://github.com/Fishwaldo/Star64_linux.git synced 2025-06-28 09:31:14 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

KVM: x86/pmu: Use different raw event masks for AMD and Intel

Browse source 
The third nybble of AMD's event select overlaps with Intel's IN_TX and
IN_TXCP bits. Therefore, we can't use AMD64_RAW_EVENT_MASK on Intel
platforms that support TSX.

Declare a raw_event_mask in the kvm_pmu structure, initialize it in
the vendor-specific pmu_refresh() functions, and use that mask for
PERF_TYPE_RAW configurations in reprogram_gp_counter().

Fixes: 710c476514 ("KVM: x86/pmu: Use AMD64_RAW_EVENT_MASK for PERF_TYPE_RAW")
Signed-off-by: Jim Mattson <jmattson@google.com>
Message-Id: <20220308012452.3468611-1-jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Jim Mattson 2022-03-07 17:24:52 -08:00 • committed by Paolo Bonzini
parent df06dae3f2
commit 95b065bf5c
4 changed files with 5 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
arch/x86/include/asm/kvm_host.h
View file

@ -511,6 +511,7 @@ struct kvm_pmu {
u64 global_ctrl_mask; u64 global_ctrl_mask;
u64 global_ovf_ctrl_mask; u64 global_ovf_ctrl_mask;
u64 reserved_bits; u64 reserved_bits;
u64 raw_event_mask;
u8 version; u8 version;
struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];

3
arch/x86/kvm/pmu.c
View file

@ -185,6 +185,7 @@ void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
u32 type = PERF_TYPE_RAW; u32 type = PERF_TYPE_RAW;
struct kvm *kvm = pmc->vcpu->kvm; struct kvm *kvm = pmc->vcpu->kvm;
struct kvm_pmu_event_filter *filter; struct kvm_pmu_event_filter *filter;
struct kvm_pmu *pmu = vcpu_to_pmu(pmc->vcpu);
bool allow_event = true; bool allow_event = true;
if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
@ -221,7 +222,7 @@ void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
} }
if (type == PERF_TYPE_RAW) if (type == PERF_TYPE_RAW)
config = eventsel & AMD64_RAW_EVENT_MASK; config = eventsel & pmu->raw_event_mask;
if (pmc->current_config == eventsel && pmc_resume_counter(pmc)) if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
return; return;

1
arch/x86/kvm/svm/pmu.c
View file

@ -284,6 +284,7 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
pmu->reserved_bits = 0xfffffff000280000ull; pmu->reserved_bits = 0xfffffff000280000ull;
pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;
pmu->version = 1; pmu->version = 1;
/* not applicable to AMD; but clean them to prevent any fall out */ /* not applicable to AMD; but clean them to prevent any fall out */
pmu->counter_bitmask[KVM_PMC_FIXED] = 0; pmu->counter_bitmask[KVM_PMC_FIXED] = 0;

1
arch/x86/kvm/vmx/pmu_intel.c
View file

@ -485,6 +485,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
pmu->counter_bitmask[KVM_PMC_FIXED] = 0; pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
pmu->version = 0; pmu->version = 0;
pmu->reserved_bits = 0xffffffff00200000ull; pmu->reserved_bits = 0xffffffff00200000ull;
pmu->raw_event_mask = X86_RAW_EVENT_MASK;
entry = kvm_find_cpuid_entry(vcpu, 0xa, 0); entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
if (!entry || !vcpu->kvm->arch.enable_pmu) if (!entry || !vcpu->kvm->arch.enable_pmu)