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clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168

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USB will drive clock from USB_PLL.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Chao Xie 2015-04-30 09:53:40 +08:00 • committed by Stephen Boyd
parent ae8d4048fa
commit a35247c6ee
4 changed files with 4 additions and 0 deletions
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1
drivers/clk/mmp/clk-of-pxa168.c
View file

@ -58,6 +58,7 @@ static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768}, {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
{PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000}, {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
{PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000}, {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
{PXA168_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
}; };
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {

1
drivers/clk/mmp/clk-of-pxa910.c
View file

@ -57,6 +57,7 @@ static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768}, {PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
{PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000}, {PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
{PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000}, {PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
{PXA910_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
}; };
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {

1
include/dt-bindings/clock/marvell,pxa168.h
View file

@ -19,6 +19,7 @@
#define PXA168_CLK_PLL1_2_1_5 19 #define PXA168_CLK_PLL1_2_1_5 19
#define PXA168_CLK_PLL1_3_16 20 #define PXA168_CLK_PLL1_3_16 20
#define PXA168_CLK_UART_PLL 27 #define PXA168_CLK_UART_PLL 27
#define PXA168_CLK_USB_PLL 28
/* apb periphrals */ /* apb periphrals */
#define PXA168_CLK_TWSI0 60 #define PXA168_CLK_TWSI0 60

1
include/dt-bindings/clock/marvell,pxa910.h
View file

@ -19,6 +19,7 @@
#define PXA910_CLK_PLL1_2_1_5 19 #define PXA910_CLK_PLL1_2_1_5 19
#define PXA910_CLK_PLL1_3_16 20 #define PXA910_CLK_PLL1_3_16 20
#define PXA910_CLK_UART_PLL 27 #define PXA910_CLK_UART_PLL 27
#define PXA910_CLK_USB_PLL 28
/* apb periphrals */ /* apb periphrals */
#define PXA910_CLK_TWSI0 60 #define PXA910_CLK_TWSI0 60