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https://github.com/Fishwaldo/Star64_linux.git
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clocksource: Add JH7110 timer driver
Add timer driver for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
This commit is contained in:
parent
0b415975de
commit
a388fc116a
3 changed files with 392 additions and 0 deletions
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@ -641,6 +641,17 @@ config RISCV_TIMER
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is accessed via both the SBI and the rdcycle instruction. This is
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required for all RISC-V systems.
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config STARFIVE_JH7110_TIMER
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bool "Timer for the STARFIVE JH7110 SoC"
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depends on ARCH_STARFIVE || COMPILE_TEST
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select TIMER_OF
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select CLKSRC_MMIO
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default ARCH_STARFIVE
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help
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This enables the timer for StarFive JH7110 SoC. On RISC-V platform,
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the system has started RISCV_TIMER, but you can also use this timer
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which can provide four channels to do a lot more things on JH7110 SoC.
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config CLINT_TIMER
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bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
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depends on GENERIC_SCHED_CLOCK && RISCV
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@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
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obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
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obj-$(CONFIG_X86_NUMACHIP) += numachip.o
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obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
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obj-$(CONFIG_STARFIVE_JH7110_TIMER) += timer-jh7110.o
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obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
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obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
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obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
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380
drivers/clocksource/timer-jh7110.c
Normal file
380
drivers/clocksource/timer-jh7110.c
Normal file
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@ -0,0 +1,380 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Starfive JH7110 Timer driver
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*
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* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
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*
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* Author:
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* Xingyu Wu <xingyu.wu@starfivetech.com>
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* Samin Guo <samin.guo@starfivetech.com>
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/sched_clock.h>
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/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
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#define JH7110_TIMER_CH_LEN 0x40
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#define JH7110_TIMER_CH_BASE(x) ((x) * JH7110_TIMER_CH_LEN)
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#define JH7110_TIMER_CH_MAX 4
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#define JH7110_CLOCK_SOURCE_RATING 200
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#define JH7110_VALID_BITS 32
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#define JH7110_DELAY_US 0
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#define JH7110_TIMEOUT_US 10000
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#define JH7110_CLOCKEVENT_RATING 300
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#define JH7110_TIMER_MAX_TICKS 0xffffffff
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#define JH7110_TIMER_MIN_TICKS 0xf
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#define JH7110_TIMER_RELOAD_VALUE 0
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#define JH7110_TIMER_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
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#define JH7110_TIMER_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
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#define JH7110_TIMER_LOAD 0x08 /* RW: load value to counter */
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#define JH7110_TIMER_ENABLE 0x10 /* RW[0]: timer enable register */
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#define JH7110_TIMER_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
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#define JH7110_TIMER_VALUE 0x18 /* RO: timer value register */
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#define JH7110_TIMER_INT_CLR 0x20 /* RW: timer interrupt clear register */
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#define JH7110_TIMER_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
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#define JH7110_TIMER_INT_CLR_ENA BIT(0)
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#define JH7110_TIMER_INT_CLR_AVA_MASK BIT(1)
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struct jh7110_clkevt {
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struct clock_event_device evt;
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struct clocksource cs;
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bool cs_is_valid;
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struct clk *clk;
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struct reset_control *rst;
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u32 rate;
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u32 reload_val;
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void __iomem *base;
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char name[sizeof("jh7110-timer.chX")];
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};
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struct jh7110_timer_priv {
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struct clk *pclk;
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struct reset_control *prst;
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struct jh7110_clkevt clkevt[JH7110_TIMER_CH_MAX];
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};
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/* 0:continuous-run mode, 1:single-run mode */
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enum jh7110_timer_mode {
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JH7110_TIMER_MODE_CONTIN,
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JH7110_TIMER_MODE_SINGLE,
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};
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/* Interrupt Mask, 0:Unmask, 1:Mask */
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enum jh7110_timer_int_mask {
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JH7110_TIMER_INT_ENA,
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JH7110_TIMER_INT_DIS,
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};
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enum jh7110_timer_enable {
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JH7110_TIMER_DIS,
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JH7110_TIMER_ENA,
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};
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static inline struct jh7110_clkevt *to_jh7110_clkevt(struct clock_event_device *evt)
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{
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return container_of(evt, struct jh7110_clkevt, evt);
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}
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/*
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* BIT(0): Read value represent channel int status.
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* Write 1 to this bit to clear interrupt. Write 0 has no effects.
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* BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
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*/
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static inline int jh7110_timer_int_clear(struct jh7110_clkevt *clkevt)
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{
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u32 value;
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int ret;
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/* Waiting interrupt can be cleared */
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ret = readl_poll_timeout_atomic(clkevt->base + JH7110_TIMER_INT_CLR, value,
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!(value & JH7110_TIMER_INT_CLR_AVA_MASK),
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JH7110_DELAY_US, JH7110_TIMEOUT_US);
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if (!ret)
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writel(JH7110_TIMER_INT_CLR_ENA, clkevt->base + JH7110_TIMER_INT_CLR);
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return ret;
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}
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static int jh7110_timer_start(struct jh7110_clkevt *clkevt)
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{
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int ret;
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/* Disable and clear interrupt first */
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writel(JH7110_TIMER_INT_DIS, clkevt->base + JH7110_TIMER_INT_MASK);
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ret = jh7110_timer_int_clear(clkevt);
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if (ret)
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return ret;
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writel(JH7110_TIMER_INT_ENA, clkevt->base + JH7110_TIMER_INT_MASK);
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writel(JH7110_TIMER_ENA, clkevt->base + JH7110_TIMER_ENABLE);
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return 0;
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}
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static int jh7110_timer_shutdown(struct clock_event_device *evt)
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{
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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writel(JH7110_TIMER_DIS, clkevt->base + JH7110_TIMER_ENABLE);
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return jh7110_timer_int_clear(clkevt);
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}
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static void jh7110_timer_suspend(struct clock_event_device *evt)
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{
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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clkevt->reload_val = readl(clkevt->base + JH7110_TIMER_LOAD);
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jh7110_timer_shutdown(evt);
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}
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static void jh7110_timer_resume(struct clock_event_device *evt)
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{
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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writel(clkevt->reload_val, clkevt->base + JH7110_TIMER_LOAD);
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writel(JH7110_TIMER_RELOAD_VALUE, clkevt->base + JH7110_TIMER_RELOAD);
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jh7110_timer_start(clkevt);
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}
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static int jh7110_timer_tick_resume(struct clock_event_device *evt)
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{
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jh7110_timer_resume(evt);
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return 0;
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}
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/* IRQ handler for the timer */
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static irqreturn_t jh7110_timer_interrupt(int irq, void *priv)
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{
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struct clock_event_device *evt = (struct clock_event_device *)priv;
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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if (jh7110_timer_int_clear(clkevt))
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return IRQ_NONE;
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if (evt->event_handler)
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int jh7110_timer_set_periodic(struct clock_event_device *evt)
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{
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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u32 periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
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writel(JH7110_TIMER_MODE_CONTIN, clkevt->base + JH7110_TIMER_CTL);
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writel(periodic, clkevt->base + JH7110_TIMER_LOAD);
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return jh7110_timer_start(clkevt);
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}
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static int jh7110_timer_set_oneshot(struct clock_event_device *evt)
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{
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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writel(JH7110_TIMER_MODE_SINGLE, clkevt->base + JH7110_TIMER_CTL);
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writel(JH7110_TIMER_MAX_TICKS, clkevt->base + JH7110_TIMER_LOAD);
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return jh7110_timer_start(clkevt);
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}
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static int jh7110_timer_set_next_event(unsigned long next,
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struct clock_event_device *evt)
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{
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struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt);
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writel(JH7110_TIMER_MODE_SINGLE, clkevt->base + JH7110_TIMER_CTL);
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writel(next, clkevt->base + JH7110_TIMER_LOAD);
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return jh7110_timer_start(clkevt);
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}
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static void jh7110_set_clockevent(struct clock_event_device *evt)
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{
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evt->features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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evt->set_state_shutdown = jh7110_timer_shutdown;
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evt->set_state_periodic = jh7110_timer_set_periodic;
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evt->set_state_oneshot = jh7110_timer_set_oneshot;
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evt->set_state_oneshot_stopped = jh7110_timer_shutdown;
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evt->tick_resume = jh7110_timer_tick_resume;
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evt->set_next_event = jh7110_timer_set_next_event;
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evt->suspend = jh7110_timer_suspend;
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evt->resume = jh7110_timer_resume;
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evt->rating = JH7110_CLOCKEVENT_RATING;
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}
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static u64 jh7110_timer_clocksource_read(struct clocksource *cs)
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{
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struct jh7110_clkevt *clkevt = container_of(cs, struct jh7110_clkevt, cs);
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return (u64)readl(clkevt->base + JH7110_TIMER_VALUE);
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}
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static int jh7110_clocksource_init(struct jh7110_clkevt *clkevt)
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{
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int ret;
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clkevt->cs.name = clkevt->name;
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clkevt->cs.rating = JH7110_CLOCK_SOURCE_RATING;
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clkevt->cs.read = jh7110_timer_clocksource_read;
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clkevt->cs.mask = CLOCKSOURCE_MASK(JH7110_VALID_BITS);
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clkevt->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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ret = clocksource_register_hz(&clkevt->cs, clkevt->rate);
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if (ret)
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return ret;
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clkevt->cs_is_valid = true; /* clocksource register done */
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writel(JH7110_TIMER_MODE_CONTIN, clkevt->base + JH7110_TIMER_CTL);
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writel(JH7110_TIMER_MAX_TICKS, clkevt->base + JH7110_TIMER_LOAD);
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return jh7110_timer_start(clkevt);
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}
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static void jh7110_clockevents_register(struct jh7110_clkevt *clkevt)
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{
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clkevt->rate = clk_get_rate(clkevt->clk);
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jh7110_set_clockevent(&clkevt->evt);
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clkevt->evt.name = clkevt->name;
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clkevt->evt.cpumask = cpu_possible_mask;
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clockevents_config_and_register(&clkevt->evt, clkevt->rate,
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JH7110_TIMER_MIN_TICKS, JH7110_TIMER_MAX_TICKS);
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}
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static void jh7110_timer_release(void *data)
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{
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struct jh7110_timer_priv *priv = data;
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int i;
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for (i = 0; i < JH7110_TIMER_CH_MAX; i++) {
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/* Disable each channel of timer */
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if (priv->clkevt[i].base)
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writel(JH7110_TIMER_DIS, priv->clkevt[i].base + JH7110_TIMER_ENABLE);
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/* Avoid no initialization in the loop of the probe */
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if (!IS_ERR_OR_NULL(priv->clkevt[i].rst))
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reset_control_assert(priv->clkevt[i].rst);
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if (priv->clkevt[i].cs_is_valid)
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clocksource_unregister(&priv->clkevt[i].cs);
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}
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reset_control_assert(priv->prst);
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}
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static int jh7110_timer_probe(struct platform_device *pdev)
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{
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struct jh7110_timer_priv *priv;
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struct jh7110_clkevt *clkevt;
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char name[sizeof("chX")];
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int ch;
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int ret;
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void __iomem *base;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return dev_err_probe(&pdev->dev, PTR_ERR(base),
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"failed to map registers\n");
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priv->prst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
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if (IS_ERR(priv->prst))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->prst),
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"failed to get apb reset\n");
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priv->pclk = devm_clk_get_enabled(&pdev->dev, "apb");
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if (IS_ERR(priv->pclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk),
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"failed to get & enable apb clock\n");
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ret = reset_control_deassert(priv->prst);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "failed to deassert apb reset\n");
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ret = devm_add_action_or_reset(&pdev->dev, jh7110_timer_release, priv);
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if (ret)
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return ret;
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for (ch = 0; ch < JH7110_TIMER_CH_MAX; ch++) {
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clkevt = &priv->clkevt[ch];
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snprintf(name, sizeof(name), "ch%d", ch);
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clkevt->base = base + JH7110_TIMER_CH_BASE(ch);
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/* Ensure timer is disabled */
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writel(JH7110_TIMER_DIS, clkevt->base + JH7110_TIMER_ENABLE);
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clkevt->rst = devm_reset_control_get_exclusive(&pdev->dev, name);
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if (IS_ERR(clkevt->rst))
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return PTR_ERR(clkevt->rst);
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clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
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if (IS_ERR(clkevt->clk))
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return PTR_ERR(clkevt->clk);
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ret = reset_control_deassert(clkevt->rst);
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if (ret)
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return ret;
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clkevt->evt.irq = platform_get_irq(pdev, ch);
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if (clkevt->evt.irq < 0)
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return clkevt->evt.irq;
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snprintf(clkevt->name, sizeof(clkevt->name), "jh7110-timer.ch%d", ch);
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jh7110_clockevents_register(clkevt);
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ret = devm_request_irq(&pdev->dev, clkevt->evt.irq, jh7110_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL,
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clkevt->name, &clkevt->evt);
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if (ret)
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return ret;
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ret = jh7110_clocksource_init(clkevt);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct of_device_id jh7110_timer_match[] = {
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{ .compatible = "starfive,jh7110-timer", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7110_timer_match);
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static struct platform_driver jh7110_timer_driver = {
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.probe = jh7110_timer_probe,
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.driver = {
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.name = "jh7110-timer",
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.of_match_table = jh7110_timer_match,
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},
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};
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module_platform_driver(jh7110_timer_driver);
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MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
|
||||
MODULE_DESCRIPTION("StarFive JH7110 timer driver");
|
||||
MODULE_LICENSE("GPL");
|
Loading…
Add table
Reference in a new issue