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pwm: sifive-ptc: Add SiFive PWM PTC driver
yiming.li: clear CNTR of PWM after setting period & duty_cycle Emil: cleanups, clock, reset and div_u64 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
This commit is contained in:
Chenjieqin
Emil Renner Berthing
parent
0f35c858ed
commit
a5c8f96c3a
3 changed files with 272 additions and 0 deletions
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@ -504,6 +504,17 @@ config PWM_SIFIVE
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To compile this driver as a module, choose M here: the module
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will be called pwm-sifive.
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config PWM_SIFIVE_PTC
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tristate "SiFive PWM PTC support"
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depends on SOC_SIFIVE || SOC_STARFIVE || COMPILE_TEST
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depends on OF
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depends on COMMON_CLK
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help
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Generic PWM framework driver for SiFive SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sifive-ptc.
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config PWM_SL28CPLD
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tristate "Kontron sl28cpld PWM support"
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depends on MFD_SL28CPLD || COMPILE_TEST
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@ -46,6 +46,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
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obj-$(CONFIG_PWM_SIFIVE_PTC) += pwm-sifive-ptc.o
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obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
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260
drivers/pwm/pwm-sifive-ptc.c
Normal file
260
drivers/pwm/pwm-sifive-ptc.c
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@ -0,0 +1,260 @@
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/*
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* Copyright (C) 2018 SiFive, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2, as published by
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* the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/reset.h>
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#include <dt-bindings/pwm/pwm.h>
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/* max channel of pwm */
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#define MAX_PWM 8
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/* PTC Register offsets */
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#define REG_RPTC_CNTR 0x0
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#define REG_RPTC_HRC 0x4
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#define REG_RPTC_LRC 0x8
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#define REG_RPTC_CTRL 0xC
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/* Bit for PWM clock */
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#define BIT_PWM_CLOCK_EN 31
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/* Bit for clock gen soft reset */
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#define BIT_CLK_GEN_SOFT_RESET 13
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#define NS_1 1000000000U
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/* Access PTC register (cntr hrc lrc and ctrl), need to replace PWM_BASE_ADDR */
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#define REG_PTC_BASE_ADDR_SUB(base, N) \
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((base) + (((N) > 3) ? (((N) - 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
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#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
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#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
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#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
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#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
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/* pwm ptc device */
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struct sifive_pwm_ptc_device {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *regs;
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};
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static inline struct sifive_pwm_ptc_device *chip_to_sifive_ptc(struct pwm_chip *c)
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{
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return container_of(c, struct sifive_pwm_ptc_device, chip);
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}
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static int sifive_pwm_ptc_get_state(struct pwm_chip *chip, struct pwm_device *dev,
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struct pwm_state *state)
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{
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struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
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u32 data_lrc;
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u32 data_hrc;
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u32 pwm_clk_ns = 0;
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/* get lrc and hrc data from registe */
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data_lrc = ioread32(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
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data_hrc = ioread32(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
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/* how many ns does apb clock elapse */
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pwm_clk_ns = NS_1 / clk_get_rate(pwm->clk);
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/* pwm period(ns) */
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state->period = data_lrc * pwm_clk_ns;
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/* duty cycle(ns) means high level eclapse ns if it is normal polarity */
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state->duty_cycle = data_hrc * pwm_clk_ns;
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/* polarity, we don't use it now because it is not in dts */
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state->polarity = PWM_POLARITY_NORMAL;
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/* enabled or not */
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state->enabled = 1;
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dev_dbg(pwm->chip.dev, "%s: no:%d\n", __func__, dev->hwpwm);
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dev_dbg(pwm->chip.dev, "data_hrc:0x%x 0x%x\n", data_hrc, data_lrc);
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dev_dbg(pwm->chip.dev, "period:%llu\n", state->period);
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dev_dbg(pwm->chip.dev, "duty_cycle:%llu\n", state->duty_cycle);
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dev_dbg(pwm->chip.dev, "polarity:%d\n", state->polarity);
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dev_dbg(pwm->chip.dev, "enabled:%d\n", state->enabled);
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return 0;
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}
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static int sifive_pwm_ptc_apply(struct pwm_chip *chip, struct pwm_device *dev,
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const struct pwm_state *state)
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{
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struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
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void __iomem *reg_addr;
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u32 pwm_clk_ns = 0;
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u32 data_hrc = 0;
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u32 data_lrc = 0;
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u32 period_data = 0;
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u32 duty_data = 0;
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dev_dbg(pwm->chip.dev, "%s: no:%d\n", __func__, dev->hwpwm);
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dev_dbg(pwm->chip.dev, "period:%llu\n", state->period);
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dev_dbg(pwm->chip.dev, "duty_cycle:%llu\n", state->duty_cycle);
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dev_dbg(pwm->chip.dev, "polarity:%d\n", state->polarity);
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dev_dbg(pwm->chip.dev, "enabled:%d\n", state->enabled);
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/* duty_cycle should be less or equal than period */
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if (state->duty_cycle > state->period)
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return -EINVAL;
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/* calculate pwm real period (ns) */
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pwm_clk_ns = NS_1 / clk_get_rate(pwm->clk);
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dev_dbg(pwm->chip.dev, "pwm_clk_ns:%u\n", pwm_clk_ns);
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/* calculate period count */
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period_data = div_u64(state->period, pwm_clk_ns);
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if (!state->enabled)
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/* if disabled, just set duty_data to 0, which means low level always */
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duty_data = 0;
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else
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/* calculate duty count */
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duty_data = div_u64(state->duty_cycle, pwm_clk_ns);
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dev_dbg(pwm->chip.dev, "period_data:%u, duty_data:%u\n",
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period_data, duty_data);
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if (state->polarity == PWM_POLARITY_NORMAL)
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/* calculate data_hrc */
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data_hrc = period_data - duty_data;
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else
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/* calculate data_hrc */
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data_hrc = duty_data;
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data_lrc = period_data;
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/* set hrc */
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reg_addr = REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm);
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dev_dbg(pwm->chip.dev, "%s: reg_addr:%p, data:%u\n",
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__func__, reg_addr, data_hrc);
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iowrite32(data_hrc, reg_addr);
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dev_dbg(pwm->chip.dev, "%s: hrc ok\n", __func__);
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/* set lrc */
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reg_addr = REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm);
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dev_dbg(pwm->chip.dev, "%s: reg_addr:%p, data:%u\n",
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__func__, reg_addr, data_lrc);
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iowrite32(data_lrc, reg_addr);
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dev_dbg(pwm->chip.dev, "%s: lrc ok\n", __func__);
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/* Clear REG_RPTC_CNTR after setting period & duty_cycle */
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reg_addr = REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm);
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iowrite32(0, reg_addr);
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return 0;
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}
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static const struct pwm_ops sifive_pwm_ptc_ops = {
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.get_state = sifive_pwm_ptc_get_state,
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.apply = sifive_pwm_ptc_apply,
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.owner = THIS_MODULE,
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};
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static void sifive_pwm_ptc_disable_action(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int sifive_pwm_ptc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct sifive_pwm_ptc_device *pwm;
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struct pwm_chip *chip;
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struct reset_control *rst;
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int ret;
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pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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platform_set_drvdata(pdev, pwm);
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chip = &pwm->chip;
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chip->dev = dev;
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chip->ops = &sifive_pwm_ptc_ops;
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/* how many parameters can be transferred to ptc, need to fix */
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chip->of_pwm_n_cells = 3;
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chip->base = -1;
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/* get pwm channels count, max value is 8 */
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ret = of_property_read_u32(node, "starfive,npwm", &chip->npwm);
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if (ret < 0 || chip->npwm > MAX_PWM)
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chip->npwm = MAX_PWM;
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dev_dbg(dev, "%s: npwm:0x%x\n", __func__, chip->npwm);
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/* get IO base address */
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pwm->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pwm->regs))
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return dev_err_probe(dev, PTR_ERR(pwm->regs),
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"Unable to map IO resources\n");
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pwm->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(pwm->clk))
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return dev_err_probe(dev, PTR_ERR(pwm->clk),
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"Unable to get controller clock\n");
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ret = clk_prepare_enable(pwm->clk);
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if (ret)
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return dev_err_probe(dev, ret, "Unable to enable clock\n");
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ret = devm_add_action_or_reset(dev, sifive_pwm_ptc_disable_action, pwm->clk);
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if (ret)
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return ret;
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rst = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(rst))
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return dev_err_probe(dev, PTR_ERR(rst), "Unable to get reset\n");
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ret = reset_control_deassert(rst);
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if (ret)
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return dev_err_probe(dev, ret, "Unable to deassert reset\n");
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/*
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* after pwmchip_add it will show up as /sys/class/pwm/pwmchip0,
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* 0 is chip->base, pwm0 can be seen after running echo 0 > export
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*/
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ret = devm_pwmchip_add(dev, chip);
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if (ret)
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return dev_err_probe(dev, ret, "cannot register PTC: %d\n", ret);
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dev_dbg(dev, "SiFive PWM PTC chip registered %d PWMs\n", chip->npwm);
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return 0;
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}
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static const struct of_device_id sifive_pwm_ptc_of_match[] = {
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{ .compatible = "starfive,pwm0" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sifive_pwm_ptc_of_match);
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static struct platform_driver sifive_pwm_ptc_driver = {
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.probe = sifive_pwm_ptc_probe,
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.driver = {
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.name = "pwm-sifive-ptc",
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.of_match_table = sifive_pwm_ptc_of_match,
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},
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};
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module_platform_driver(sifive_pwm_ptc_driver);
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MODULE_DESCRIPTION("SiFive PWM PTC driver");
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MODULE_LICENSE("GPL v2");
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