mirror of
https://github.com/Fishwaldo/Star64_linux.git
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Merge branch 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (59 commits) x86/gart: Do not select AGP for GART_IOMMU x86/amd-iommu: Initialize passthrough mode when requested x86/amd-iommu: Don't detach device from pt domain on driver unbind x86/amd-iommu: Make sure a device is assigned in passthrough mode x86/amd-iommu: Align locking between attach_device and detach_device x86/amd-iommu: Fix device table write order x86/amd-iommu: Add passthrough mode initialization functions x86/amd-iommu: Add core functions for pd allocation/freeing x86/dma: Mark iommu_pass_through as __read_mostly x86/amd-iommu: Change iommu_map_page to support multiple page sizes x86/amd-iommu: Support higher level PTEs in iommu_page_unmap x86/amd-iommu: Remove old page table handling macros x86/amd-iommu: Use 2-level page tables for dma_ops domains x86/amd-iommu: Remove bus_addr check in iommu_map_page x86/amd-iommu: Remove last usages of IOMMU_PTE_L0_INDEX x86/amd-iommu: Change alloc_pte to support 64 bit address space x86/amd-iommu: Introduce increase_address_space function x86/amd-iommu: Flush domains if address space size was increased x86/amd-iommu: Introduce set_dte_entry function x86/amd-iommu: Add a gneric version of amd_iommu_flush_all_devices ...
This commit is contained in:
Linus Torvalds
commit
a66a50054e
29 changed files with 724 additions and 967 deletions
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@ -3,6 +3,7 @@
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#include <linux/scatterlist.h>
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#include <linux/mm.h>
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#include <linux/dma-debug.h>
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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@ -13,142 +14,40 @@ extern int dma_set_mask(struct device *dev, u64 dma_mask);
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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struct dma_ops {
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void *(*alloc_coherent)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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void (*free_coherent)(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle);
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dma_addr_t (*map_page)(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction);
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void (*unmap_page)(struct device *dev, dma_addr_t dma_addr,
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size_t size,
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enum dma_data_direction direction);
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int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction);
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void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
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int nhwentries,
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enum dma_data_direction direction);
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void (*sync_single_for_cpu)(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction);
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void (*sync_single_for_device)(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction);
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void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
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int nelems,
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enum dma_data_direction direction);
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void (*sync_sg_for_device)(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction dir);
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};
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extern const struct dma_ops *dma_ops;
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extern struct dma_map_ops *dma_ops, pci32_dma_ops;
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extern struct bus_type pci_bus_type;
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static inline struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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#if defined(CONFIG_SPARC32) && defined(CONFIG_PCI)
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if (dev->bus == &pci_bus_type)
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return &pci32_dma_ops;
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#endif
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return dma_ops;
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}
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#include <asm-generic/dma-mapping-common.h>
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
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struct dma_map_ops *ops = get_dma_ops(dev);
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void *cpu_addr;
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cpu_addr = ops->alloc_coherent(dev, size, dma_handle, flag);
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debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
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return cpu_addr;
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle)
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{
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dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
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}
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struct dma_map_ops *ops = get_dma_ops(dev);
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static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
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size_t size,
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enum dma_data_direction direction)
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{
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return dma_ops->map_page(dev, virt_to_page(cpu_addr),
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(unsigned long)cpu_addr & ~PAGE_MASK, size,
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direction);
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debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
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ops->free_coherent(dev, size, cpu_addr, dma_handle);
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}
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static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_ops->unmap_page(dev, dma_addr, size, direction);
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}
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static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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return dma_ops->map_page(dev, page, offset, size, direction);
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}
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static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_ops->unmap_page(dev, dma_address, size, direction);
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}
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static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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return dma_ops->map_sg(dev, sg, nents, direction);
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}
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static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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dma_ops->unmap_sg(dev, sg, nents, direction);
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}
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static inline void dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
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}
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static inline void dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction direction)
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{
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if (dma_ops->sync_single_for_device)
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dma_ops->sync_single_for_device(dev, dma_handle, size,
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direction);
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}
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static inline void dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
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}
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static inline void dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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if (dma_ops->sync_sg_for_device)
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dma_ops->sync_sg_for_device(dev, sg, nelems, direction);
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}
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static inline void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single_for_cpu(dev, dma_handle+offset, size, dir);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single_for_device(dev, dma_handle+offset, size, dir);
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}
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return (dma_addr == DMA_ERROR_CODE);
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@ -5,4 +5,7 @@
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#else
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#include <asm/pci_32.h>
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#endif
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#include <asm-generic/pci-dma-compat.h>
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#endif
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@ -31,42 +31,8 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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#include <asm/scatterlist.h>
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struct pci_dev;
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/* Allocate and map kernel buffer using consistent mode DMA for a device.
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* hwdev should be valid struct pci_dev pointer for PCI devices.
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*/
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extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
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/* Free and unmap a consistent DMA buffer.
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* cpu_addr is what was returned from pci_alloc_consistent,
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* size must be the same as what as passed into pci_alloc_consistent,
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* and likewise dma_addr must be the same as what *dma_addrp was set to.
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*
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* References to the memory and mappings assosciated with cpu_addr/dma_addr
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* past this call are illegal.
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*/
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extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
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/* Map a single buffer of the indicated size for DMA in streaming mode.
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* The 32-bit bus address to use is returned.
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*
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* Once the device is given the dma address, the device owns this memory
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* until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
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*/
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extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
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/* Unmap a single streaming mode DMA translation. The dma_addr and size
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* must match what was provided for in a previous pci_map_single call. All
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* other usages are undefined.
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*
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* After this call, reads by the cpu to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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@ -81,69 +47,6 @@ extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/*
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* Same as above, only with pages instead of mapped addresses.
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*/
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extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
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unsigned long offset, size_t size, int direction);
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extern void pci_unmap_page(struct pci_dev *hwdev,
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dma_addr_t dma_address, size_t size, int direction);
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/* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scather-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
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/* Unmap a set of streaming mode DMA translations.
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* Again, cpu read rules concerning calls here are the same as for
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* pci_unmap_single() above.
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*/
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extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
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/* Make physical memory consistent for a single
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* streaming mode DMA translation after a transfer.
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*
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* If you perform a pci_map_single() but wish to interrogate the
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* buffer using the cpu, yet do not wish to teardown the PCI dma
|
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* mapping, you must call this function before doing so. At the
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* next point you give the PCI dma address back to the card, you
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* must first perform a pci_dma_sync_for_device, and then the device
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* again owns the buffer.
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*/
|
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extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
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extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
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|
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/* Make physical memory consistent for a set of streaming
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* mode DMA translations after a transfer.
|
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*
|
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* The same as pci_dma_sync_single_* but for a scatter-gather list,
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* same rules and usage.
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*/
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extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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|
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/* Return whether the given PCI device DMA address mask can
|
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* be supported properly. For example, if your device can
|
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* only drive the low 24-bits during PCI bus mastering, then
|
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* you would pass 0x00ffffff as the mask to this function.
|
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*/
|
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static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
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{
|
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return 1;
|
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}
|
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|
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#ifdef CONFIG_PCI
|
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
|
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enum pci_dma_burst_strategy *strat,
|
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|
|
@ -154,14 +57,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
|
|||
}
|
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#endif
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|
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#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
|
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|
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static inline int pci_dma_mapping_error(struct pci_dev *pdev,
|
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dma_addr_t dma_addr)
|
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{
|
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return (dma_addr == PCI_DMA_ERROR_CODE);
|
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}
|
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|
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struct device_node;
|
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extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
|
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|
||||
|
|
|
|||
|
|
@ -35,37 +35,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
|
|||
*/
|
||||
#define PCI_DMA_BUS_IS_PHYS (0)
|
||||
|
||||
static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
|
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dma_addr_t *dma_handle)
|
||||
{
|
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return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
|
||||
}
|
||||
|
||||
static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
|
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void *vaddr, dma_addr_t dma_handle)
|
||||
{
|
||||
return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
|
||||
}
|
||||
|
||||
static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
|
||||
size_t size, int direction)
|
||||
{
|
||||
return dma_map_single(&pdev->dev, ptr, size,
|
||||
(enum dma_data_direction) direction);
|
||||
}
|
||||
|
||||
static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
|
||||
size_t size, int direction)
|
||||
{
|
||||
dma_unmap_single(&pdev->dev, dma_addr, size,
|
||||
(enum dma_data_direction) direction);
|
||||
}
|
||||
|
||||
#define pci_map_page(dev, page, off, size, dir) \
|
||||
pci_map_single(dev, (page_address(page) + (off)), size, dir)
|
||||
#define pci_unmap_page(dev,addr,sz,dir) \
|
||||
pci_unmap_single(dev,addr,sz,dir)
|
||||
|
||||
/* pci_unmap_{single,page} is not a nop, thus... */
|
||||
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
|
||||
dma_addr_t ADDR_NAME;
|
||||
|
|
@ -80,57 +49,6 @@ static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
|
|||
#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
|
||||
(((PTR)->LEN_NAME) = (VAL))
|
||||
|
||||
static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
|
||||
int nents, int direction)
|
||||
{
|
||||
return dma_map_sg(&pdev->dev, sg, nents,
|
||||
(enum dma_data_direction) direction);
|
||||
}
|
||||
|
||||
static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
|
||||
int nents, int direction)
|
||||
{
|
||||
dma_unmap_sg(&pdev->dev, sg, nents,
|
||||
(enum dma_data_direction) direction);
|
||||
}
|
||||
|
||||
static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
|
||||
dma_addr_t dma_handle,
|
||||
size_t size, int direction)
|
||||
{
|
||||
dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
|
||||
(enum dma_data_direction) direction);
|
||||
}
|
||||
|
||||
static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
|
||||
dma_addr_t dma_handle,
|
||||
size_t size, int direction)
|
||||
{
|
||||
/* No flushing needed to sync cpu writes to the device. */
|
||||
}
|
||||
|
||||
static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
|
||||
struct scatterlist *sg,
|
||||
int nents, int direction)
|
||||
{
|
||||
dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
|
||||
(enum dma_data_direction) direction);
|
||||
}
|
||||
|
||||
static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
|
||||
struct scatterlist *sg,
|
||||
int nelems, int direction)
|
||||
{
|
||||
/* No flushing needed to sync cpu writes to the device. */
|
||||
}
|
||||
|
||||
/* Return whether the given PCI device DMA address mask can
|
||||
* be supported properly. For example, if your device can
|
||||
* only drive the low 24-bits during PCI bus mastering, then
|
||||
* you would pass 0x00ffffff as the mask to this function.
|
||||
*/
|
||||
extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
|
||||
|
||||
/* PCI IOMMU mapping bypass support. */
|
||||
|
||||
/* PCI 64-bit addressing works for all slots on all controller
|
||||
|
|
@ -140,12 +58,6 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
|
|||
#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
|
||||
#define PCI64_ADDR_BASE 0xfffc000000000000UL
|
||||
|
||||
static inline int pci_dma_mapping_error(struct pci_dev *pdev,
|
||||
dma_addr_t dma_addr)
|
||||
{
|
||||
return dma_mapping_error(&pdev->dev, dma_addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
|
||||
enum pci_dma_burst_strategy *strat,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue