mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-03-16 12:14:06 +00:00
dmaengine: hisilicon: Fix CQ head update
[ Upstream commit94477a79cf
] After completion of data transfer of one or multiple descriptors, the completion status and the current head pointer to submission queue are written into the CQ and interrupt can be generated to inform the software. In interrupt process CQ is read and cq_head is updated. hisi_dma_irq updates cq_head only when the completion status is success. When an abnormal interrupt reports, cq_head will not update which will cause subsequent interrupt processes read the error CQ and never report the correct status. This patch updates cq_head whenever CQ is accessed. Fixes:e9f08b6525
("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-3-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
2c2749a4f1
commit
b24befa131
1 changed files with 3 additions and 5 deletions
|
@ -436,12 +436,10 @@ static irqreturn_t hisi_dma_irq(int irq, void *data)
|
|||
desc = chan->desc;
|
||||
cqe = chan->cq + chan->cq_head;
|
||||
if (desc) {
|
||||
chan->cq_head = (chan->cq_head + 1) % hdma_dev->chan_depth;
|
||||
hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR,
|
||||
chan->qp_num, chan->cq_head);
|
||||
if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
|
||||
chan->cq_head = (chan->cq_head + 1) %
|
||||
hdma_dev->chan_depth;
|
||||
hisi_dma_chan_write(hdma_dev->base,
|
||||
HISI_DMA_CQ_HEAD_PTR, chan->qp_num,
|
||||
chan->cq_head);
|
||||
vchan_cookie_complete(&desc->vd);
|
||||
} else {
|
||||
dev_err(&hdma_dev->pdev->dev, "task error!\n");
|
||||
|
|
Loading…
Add table
Reference in a new issue