mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-03-17 20:54:10 +00:00
- Tweak initia DPCD backlight.enabled value (Sean)
- Initialize reserved MOCS indices (Ayaz) - Mark initial fb obj as WT on eLLC machines to avoid rcu lockup (Ville) - Support parsing of oversize batches (Chris) - Delay execlists processing for TGL (Chris) - Use the active reference on the vma during error capture (Chris) - Widen CSB pointer (Chris) - Wait for CSB entries on TGL (Chris) - Fix unwind for scratch page allocation (Chris) - Exclude low patches of stolen memory (Chris) - Force VT'd workarounds when running as a guest OS (Chris) - Drop runtime-pm assert from vpgu io accessors (Chris) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAl+R8a4ACgkQ+mJfZA7r E8oazwgAu+NP5GlIHTcG6bV4vxRaEDdlDf3uH+ENOGfRT0PoX6qVNpkdc/nmTZC/ RFzHVsKJi1zXS9XetP33YKZ7KFPZxJMXdhGSu+f08Q6nf0jBdFUm3mhnrDWoLO9+ fS88L4HqXREvBLDctN89akuZ1/pZ3p0KsBqAOuP+LjRAsquHgIP3eUzwZMVbTgTZ KLojKMHHrZxRtynMFrW6JO+gBok+mGydpOp7F1bK4jSmOIlYA5OsIW3xn9+Ytveu 9Od/yIjKeCyPD64ncz8wcbcPxZhnXENzZElBYT6sQSHDZ9wNCOUhfJT0v8t8G5So vzOvf2YXa+2IKiGY2sd2ov9svz3Wgg== =oidT -----END PGP SIGNATURE----- Merge tag 'drm-intel-next-fixes-2020-10-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Tweak initia DPCD backlight.enabled value (Sean) - Initialize reserved MOCS indices (Ayaz) - Mark initial fb obj as WT on eLLC machines to avoid rcu lockup (Ville) - Support parsing of oversize batches (Chris) - Delay execlists processing for TGL (Chris) - Use the active reference on the vma during error capture (Chris) - Widen CSB pointer (Chris) - Wait for CSB entries on TGL (Chris) - Fix unwind for scratch page allocation (Chris) - Exclude low patches of stolen memory (Chris) - Force VT'd workarounds when running as a guest OS (Chris) - Drop runtime-pm assert from vpgu io accessors (Chris) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201022205613.GA3469192@intel.com
This commit is contained in:
commit
b45b6fbc67
15 changed files with 335 additions and 54 deletions
|
@ -153,6 +153,7 @@ config DRM_I915_SELFTEST
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select DRM_EXPORT_FOR_TESTS if m
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select FAULT_INJECTION
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select PRIME_NUMBERS
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select CRC32
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help
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Choose this option to allow the driver to perform selftests upon
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loading; also requires the i915.selftest=1 module parameter. To
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|
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@ -3434,6 +3434,14 @@ initial_plane_vma(struct drm_i915_private *i915,
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if (IS_ERR(obj))
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return NULL;
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/*
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* Mark it WT ahead of time to avoid changing the
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* cache_level during fbdev initialization. The
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* unbind there would get stuck waiting for rcu.
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*/
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i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
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I915_CACHE_WT : I915_CACHE_NONE);
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switch (plane_config->tiling) {
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case I915_TILING_NONE:
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break;
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@ -52,6 +52,25 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
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}
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}
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static bool intel_dp_aux_backlight_dpcd_mode(struct intel_connector *connector)
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{
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struct intel_dp *intel_dp = intel_attached_dp(connector);
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 mode_reg;
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
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&mode_reg) != 1) {
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drm_dbg_kms(&i915->drm,
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"Failed to read the DPCD register 0x%x\n",
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
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return false;
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}
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return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
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DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
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}
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/*
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* Read the current backlight value from DPCD register(s) based
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* on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
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@ -61,24 +80,13 @@ static u32 intel_dp_aux_get_backlight(struct intel_connector *connector)
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struct intel_dp *intel_dp = intel_attached_dp(connector);
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 read_val[2] = { 0x0 };
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u8 mode_reg;
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u16 level = 0;
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
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&mode_reg) != 1) {
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drm_dbg_kms(&i915->drm,
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"Failed to read the DPCD register 0x%x\n",
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
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return 0;
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}
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/*
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* If we're not in DPCD control mode yet, the programmed brightness
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* value is meaningless and we should assume max brightness
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*/
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if ((mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) !=
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DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD)
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if (!intel_dp_aux_backlight_dpcd_mode(connector))
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return connector->panel.backlight.max;
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if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
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@ -319,7 +327,8 @@ static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
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panel->backlight.min = 0;
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panel->backlight.level = intel_dp_aux_get_backlight(connector);
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panel->backlight.enabled = panel->backlight.level != 0;
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panel->backlight.enabled = intel_dp_aux_backlight_dpcd_mode(connector) &&
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panel->backlight.level != 0;
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return 0;
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}
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@ -287,8 +287,8 @@ struct i915_execbuffer {
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u64 invalid_flags; /** Set of execobj.flags that are invalid */
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u32 context_flags; /** Set of execobj.flags to insert from the ctx */
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u64 batch_len; /** Length of batch within object */
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u32 batch_start_offset; /** Location within object of batch */
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u32 batch_len; /** Length of batch within object */
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u32 batch_flags; /** Flags composed for emit_bb_start() */
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struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
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@ -871,6 +871,10 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
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if (eb->batch_len == 0)
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eb->batch_len = eb->batch->vma->size - eb->batch_start_offset;
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if (unlikely(eb->batch_len == 0)) { /* impossible! */
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drm_dbg(&i915->drm, "Invalid batch length\n");
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return -EINVAL;
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}
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return 0;
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@ -2424,7 +2428,7 @@ static int eb_parse(struct i915_execbuffer *eb)
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struct drm_i915_private *i915 = eb->i915;
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struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
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struct i915_vma *shadow, *trampoline, *batch;
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unsigned int len;
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unsigned long len;
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int err;
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if (!eb_use_cmdparser(eb)) {
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@ -2449,6 +2453,8 @@ static int eb_parse(struct i915_execbuffer *eb)
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} else {
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len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
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}
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if (unlikely(len < eb->batch_len)) /* last paranoid check of overflow */
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return -EINVAL;
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if (!pool) {
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pool = intel_gt_get_buffer_pool(eb->engine->gt, len);
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@ -53,8 +53,10 @@ int i915_gem_stolen_insert_node(struct drm_i915_private *i915,
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struct drm_mm_node *node, u64 size,
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unsigned alignment)
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{
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return i915_gem_stolen_insert_node_in_range(i915, node, size,
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alignment, 0, U64_MAX);
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return i915_gem_stolen_insert_node_in_range(i915, node,
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size, alignment,
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I915_GEM_STOLEN_BIAS,
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U64_MAX);
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}
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void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
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@ -30,4 +30,6 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv
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resource_size_t stolen_offset,
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resource_size_t size);
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#define I915_GEM_STOLEN_BIAS SZ_128K
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#endif /* __I915_GEM_STOLEN_H__ */
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@ -239,18 +239,24 @@ static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt)
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I915_CACHE_NONE, PTE_READ_ONLY);
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vm->scratch[1] = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
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if (IS_ERR(vm->scratch[1]))
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return PTR_ERR(vm->scratch[1]);
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if (IS_ERR(vm->scratch[1])) {
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ret = PTR_ERR(vm->scratch[1]);
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goto err_scratch0;
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}
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ret = pin_pt_dma(vm, vm->scratch[1]);
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if (ret) {
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i915_gem_object_put(vm->scratch[1]);
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return ret;
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}
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if (ret)
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goto err_scratch1;
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fill32_px(vm->scratch[1], vm->scratch[0]->encode);
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return 0;
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err_scratch1:
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i915_gem_object_put(vm->scratch[1]);
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err_scratch0:
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i915_gem_object_put(vm->scratch[0]);
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return ret;
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}
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static void gen6_ppgtt_free_pd(struct gen6_ppgtt *ppgtt)
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@ -604,7 +604,8 @@ static int gen8_init_scratch(struct i915_address_space *vm)
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return 0;
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free_scratch:
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free_scratch(vm);
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while (i--)
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i915_gem_object_put(vm->scratch[i]);
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return -ENOMEM;
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}
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@ -278,7 +278,7 @@ struct intel_engine_execlists {
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*
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* Note these register may be either mmio or HWSP shadow.
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*/
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u32 *csb_status;
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u64 *csb_status;
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/**
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* @csb_size: context status buffer FIFO size
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@ -1140,9 +1140,8 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
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/* Check in case we rollback so far we wrap [size/2] */
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if (intel_ring_direction(rq->ring,
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intel_ring_wrap(rq->ring,
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rq->tail),
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rq->ring->tail) > 0)
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rq->tail,
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rq->ring->tail + 8) > 0)
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rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
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active = rq;
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@ -2464,7 +2463,7 @@ cancel_port_requests(struct intel_engine_execlists * const execlists)
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}
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static inline void
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invalidate_csb_entries(const u32 *first, const u32 *last)
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invalidate_csb_entries(const u64 *first, const u64 *last)
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{
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clflush((void *)first);
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clflush((void *)last);
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@ -2496,14 +2495,25 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
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* bits 47-57: sw context id of the lrc the GT switched away from
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* bits 58-63: sw counter of the lrc the GT switched away from
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*/
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static inline bool
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gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
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static inline bool gen12_csb_parse(const u64 *csb)
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{
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u32 lower_dw = csb[0];
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u32 upper_dw = csb[1];
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bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw);
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bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw);
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bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
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bool ctx_away_valid;
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bool new_queue;
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u64 entry;
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/* HSD#22011248461 */
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entry = READ_ONCE(*csb);
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if (unlikely(entry == -1)) {
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preempt_disable();
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if (wait_for_atomic_us((entry = READ_ONCE(*csb)) != -1, 50))
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GEM_WARN_ON("50us CSB timeout");
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preempt_enable();
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}
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WRITE_ONCE(*(u64 *)csb, -1);
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ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(entry));
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new_queue =
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lower_32_bits(entry) & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
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/*
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* The context switch detail is not guaranteed to be 5 when a preemption
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@ -2513,7 +2523,7 @@ gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
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* would require some extra handling, but we don't support that.
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*/
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if (!ctx_away_valid || new_queue) {
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GEM_BUG_ON(!ctx_to_valid);
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GEM_BUG_ON(!GEN12_CSB_CTX_VALID(lower_32_bits(entry)));
|
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return true;
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}
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|
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|
@ -2522,12 +2532,11 @@ gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
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* context switch on an unsuccessful wait instruction since we always
|
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* use polling mode.
|
||||
*/
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GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw));
|
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GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_32_bits(entry)));
|
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return false;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
gen8_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
|
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static inline bool gen8_csb_parse(const u64 *csb)
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{
|
||||
return *csb & (GEN8_CTX_STATUS_IDLE_ACTIVE | GEN8_CTX_STATUS_PREEMPTED);
|
||||
}
|
||||
|
@ -2535,7 +2544,7 @@ gen8_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
|
|||
static void process_csb(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct intel_engine_execlists * const execlists = &engine->execlists;
|
||||
const u32 * const buf = execlists->csb_status;
|
||||
const u64 * const buf = execlists->csb_status;
|
||||
const u8 num_entries = execlists->csb_size;
|
||||
u8 head, tail;
|
||||
|
||||
|
@ -2616,12 +2625,14 @@ static void process_csb(struct intel_engine_cs *engine)
|
|||
*/
|
||||
|
||||
ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
|
||||
head, buf[2 * head + 0], buf[2 * head + 1]);
|
||||
head,
|
||||
upper_32_bits(buf[head]),
|
||||
lower_32_bits(buf[head]));
|
||||
|
||||
if (INTEL_GEN(engine->i915) >= 12)
|
||||
promote = gen12_csb_parse(execlists, buf + 2 * head);
|
||||
promote = gen12_csb_parse(buf + head);
|
||||
else
|
||||
promote = gen8_csb_parse(execlists, buf + 2 * head);
|
||||
promote = gen8_csb_parse(buf + head);
|
||||
if (promote) {
|
||||
struct i915_request * const *old = execlists->active;
|
||||
|
||||
|
@ -2649,6 +2660,9 @@ static void process_csb(struct intel_engine_cs *engine)
|
|||
smp_wmb(); /* complete the seqlock */
|
||||
WRITE_ONCE(execlists->active, execlists->inflight);
|
||||
|
||||
/* XXX Magic delay for tgl */
|
||||
ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
|
||||
|
||||
WRITE_ONCE(execlists->pending[0], NULL);
|
||||
} else {
|
||||
if (GEM_WARN_ON(!*execlists->active)) {
|
||||
|
@ -4005,6 +4019,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
|
|||
WRITE_ONCE(*execlists->csb_write, reset_value);
|
||||
wmb(); /* Make sure this is visible to HW (paranoia?) */
|
||||
|
||||
/* Check that the GPU does indeed update the CSB entries! */
|
||||
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
|
||||
invalidate_csb_entries(&execlists->csb_status[0],
|
||||
&execlists->csb_status[reset_value]);
|
||||
|
||||
|
@ -5157,7 +5173,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
|
|||
}
|
||||
|
||||
execlists->csb_status =
|
||||
&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
|
||||
(u64 *)&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
|
||||
|
||||
execlists->csb_write =
|
||||
&engine->status_page.addr[intel_hws_csb_write_index(i915)];
|
||||
|
|
|
@ -234,11 +234,17 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
|
|||
L3_1_UC)
|
||||
|
||||
static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
|
||||
/* Base - Error (Reserved for Non-Use) */
|
||||
MOCS_ENTRY(0, 0x0, 0x0),
|
||||
/* Base - Reserved */
|
||||
MOCS_ENTRY(1, 0x0, 0x0),
|
||||
|
||||
/*
|
||||
* NOTE:
|
||||
* Reserved and unspecified MOCS indices have been set to (L3 + LCC).
|
||||
* These reserved entries should never be used, they may be changed
|
||||
* to low performant variants with better coherency in the future if
|
||||
* more entries are needed. We are programming index I915_MOCS_PTE(1)
|
||||
* only, __init_mocs_table() take care to program unused index with
|
||||
* this entry.
|
||||
*/
|
||||
MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
|
||||
L3_3_WB),
|
||||
GEN11_MOCS_ENTRIES,
|
||||
|
||||
/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
|
||||
|
|
|
@ -3,9 +3,203 @@
|
|||
* Copyright © 2018 Intel Corporation
|
||||
*/
|
||||
|
||||
#include <linux/crc32.h>
|
||||
|
||||
#include "gem/i915_gem_stolen.h"
|
||||
|
||||
#include "i915_memcpy.h"
|
||||
#include "i915_selftest.h"
|
||||
#include "selftests/igt_reset.h"
|
||||
#include "selftests/igt_atomic.h"
|
||||
#include "selftests/igt_spinner.h"
|
||||
|
||||
static int
|
||||
__igt_reset_stolen(struct intel_gt *gt,
|
||||
intel_engine_mask_t mask,
|
||||
const char *msg)
|
||||
{
|
||||
struct i915_ggtt *ggtt = >->i915->ggtt;
|
||||
const struct resource *dsm = >->i915->dsm;
|
||||
resource_size_t num_pages, page;
|
||||
struct intel_engine_cs *engine;
|
||||
intel_wakeref_t wakeref;
|
||||
enum intel_engine_id id;
|
||||
struct igt_spinner spin;
|
||||
long max, count;
|
||||
void *tmp;
|
||||
u32 *crc;
|
||||
int err;
|
||||
|
||||
if (!drm_mm_node_allocated(&ggtt->error_capture))
|
||||
return 0;
|
||||
|
||||
num_pages = resource_size(dsm) >> PAGE_SHIFT;
|
||||
if (!num_pages)
|
||||
return 0;
|
||||
|
||||
crc = kmalloc_array(num_pages, sizeof(u32), GFP_KERNEL);
|
||||
if (!crc)
|
||||
return -ENOMEM;
|
||||
|
||||
tmp = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
if (!tmp) {
|
||||
err = -ENOMEM;
|
||||
goto err_crc;
|
||||
}
|
||||
|
||||
igt_global_reset_lock(gt);
|
||||
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
|
||||
|
||||
err = igt_spinner_init(&spin, gt);
|
||||
if (err)
|
||||
goto err_lock;
|
||||
|
||||
for_each_engine(engine, gt, id) {
|
||||
struct intel_context *ce;
|
||||
struct i915_request *rq;
|
||||
|
||||
if (!(mask & engine->mask))
|
||||
continue;
|
||||
|
||||
if (!intel_engine_can_store_dword(engine))
|
||||
continue;
|
||||
|
||||
ce = intel_context_create(engine);
|
||||
if (IS_ERR(ce)) {
|
||||
err = PTR_ERR(ce);
|
||||
goto err_spin;
|
||||
}
|
||||
rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK);
|
||||
intel_context_put(ce);
|
||||
if (IS_ERR(rq)) {
|
||||
err = PTR_ERR(rq);
|
||||
goto err_spin;
|
||||
}
|
||||
i915_request_add(rq);
|
||||
}
|
||||
|
||||
for (page = 0; page < num_pages; page++) {
|
||||
dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT);
|
||||
void __iomem *s;
|
||||
void *in;
|
||||
|
||||
ggtt->vm.insert_page(&ggtt->vm, dma,
|
||||
ggtt->error_capture.start,
|
||||
I915_CACHE_NONE, 0);
|
||||
mb();
|
||||
|
||||
s = io_mapping_map_wc(&ggtt->iomap,
|
||||
ggtt->error_capture.start,
|
||||
PAGE_SIZE);
|
||||
|
||||
if (!__drm_mm_interval_first(>->i915->mm.stolen,
|
||||
page << PAGE_SHIFT,
|
||||
((page + 1) << PAGE_SHIFT) - 1))
|
||||
memset32(s, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
|
||||
|
||||
in = s;
|
||||
if (i915_memcpy_from_wc(tmp, s, PAGE_SIZE))
|
||||
in = tmp;
|
||||
crc[page] = crc32_le(0, in, PAGE_SIZE);
|
||||
|
||||
io_mapping_unmap(s);
|
||||
}
|
||||
mb();
|
||||
ggtt->vm.clear_range(&ggtt->vm, ggtt->error_capture.start, PAGE_SIZE);
|
||||
|
||||
if (mask == ALL_ENGINES) {
|
||||
intel_gt_reset(gt, mask, NULL);
|
||||
} else {
|
||||
for_each_engine(engine, gt, id) {
|
||||
if (mask & engine->mask)
|
||||
intel_engine_reset(engine, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
max = -1;
|
||||
count = 0;
|
||||
for (page = 0; page < num_pages; page++) {
|
||||
dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT);
|
||||
void __iomem *s;
|
||||
void *in;
|
||||
u32 x;
|
||||
|
||||
ggtt->vm.insert_page(&ggtt->vm, dma,
|
||||
ggtt->error_capture.start,
|
||||
I915_CACHE_NONE, 0);
|
||||
mb();
|
||||
|
||||
s = io_mapping_map_wc(&ggtt->iomap,
|
||||
ggtt->error_capture.start,
|
||||
PAGE_SIZE);
|
||||
|
||||
in = s;
|
||||
if (i915_memcpy_from_wc(tmp, s, PAGE_SIZE))
|
||||
in = tmp;
|
||||
x = crc32_le(0, in, PAGE_SIZE);
|
||||
|
||||
if (x != crc[page] &&
|
||||
!__drm_mm_interval_first(>->i915->mm.stolen,
|
||||
page << PAGE_SHIFT,
|
||||
((page + 1) << PAGE_SHIFT) - 1)) {
|
||||
pr_debug("unused stolen page %pa modified by GPU reset\n",
|
||||
&page);
|
||||
if (count++ == 0)
|
||||
igt_hexdump(in, PAGE_SIZE);
|
||||
max = page;
|
||||
}
|
||||
|
||||
io_mapping_unmap(s);
|
||||
}
|
||||
mb();
|
||||
ggtt->vm.clear_range(&ggtt->vm, ggtt->error_capture.start, PAGE_SIZE);
|
||||
|
||||
if (count > 0) {
|
||||
pr_info("%s reset clobbered %ld pages of stolen, last clobber at page %ld\n",
|
||||
msg, count, max);
|
||||
}
|
||||
if (max >= I915_GEM_STOLEN_BIAS >> PAGE_SHIFT) {
|
||||
pr_err("%s reset clobbered unreserved area [above %x] of stolen; may cause severe faults\n",
|
||||
msg, I915_GEM_STOLEN_BIAS);
|
||||
err = -EINVAL;
|
||||
}
|
||||
|
||||
err_spin:
|
||||
igt_spinner_fini(&spin);
|
||||
|
||||
err_lock:
|
||||
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
|
||||
igt_global_reset_unlock(gt);
|
||||
|
||||
kfree(tmp);
|
||||
err_crc:
|
||||
kfree(crc);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int igt_reset_device_stolen(void *arg)
|
||||
{
|
||||
return __igt_reset_stolen(arg, ALL_ENGINES, "device");
|
||||
}
|
||||
|
||||
static int igt_reset_engines_stolen(void *arg)
|
||||
{
|
||||
struct intel_gt *gt = arg;
|
||||
struct intel_engine_cs *engine;
|
||||
enum intel_engine_id id;
|
||||
int err;
|
||||
|
||||
if (!intel_has_reset_engine(gt))
|
||||
return 0;
|
||||
|
||||
for_each_engine(engine, gt, id) {
|
||||
err = __igt_reset_stolen(gt, engine->mask, engine->name);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int igt_global_reset(void *arg)
|
||||
{
|
||||
|
@ -164,6 +358,8 @@ int intel_reset_live_selftests(struct drm_i915_private *i915)
|
|||
{
|
||||
static const struct i915_subtest tests[] = {
|
||||
SUBTEST(igt_global_reset), /* attempt to recover GPU first */
|
||||
SUBTEST(igt_reset_device_stolen),
|
||||
SUBTEST(igt_reset_engines_stolen),
|
||||
SUBTEST(igt_wedged_reset),
|
||||
SUBTEST(igt_atomic_reset),
|
||||
SUBTEST(igt_atomic_engine_reset),
|
||||
|
|
|
@ -33,6 +33,8 @@
|
|||
#include <uapi/drm/i915_drm.h>
|
||||
#include <uapi/drm/drm_fourcc.h>
|
||||
|
||||
#include <asm/hypervisor.h>
|
||||
|
||||
#include <linux/io-mapping.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-algo-bit.h>
|
||||
|
@ -1760,7 +1762,9 @@ static inline bool intel_vtd_active(void)
|
|||
if (intel_iommu_gfx_mapped)
|
||||
return true;
|
||||
#endif
|
||||
return false;
|
||||
|
||||
/* Running as a guest, we assume the host is enforcing VT'd */
|
||||
return !hypervisor_is_type(X86_HYPER_NATIVE);
|
||||
}
|
||||
|
||||
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
|
||||
|
|
|
@ -1312,7 +1312,7 @@ capture_vma(struct intel_engine_capture_vma *next,
|
|||
}
|
||||
|
||||
strcpy(c->name, name);
|
||||
c->vma = i915_vma_get(vma);
|
||||
c->vma = vma; /* reference held while active */
|
||||
|
||||
c->next = next;
|
||||
return c;
|
||||
|
@ -1402,7 +1402,6 @@ intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
|
|||
compress));
|
||||
|
||||
i915_active_release(&vma->active);
|
||||
i915_vma_put(vma);
|
||||
|
||||
capture = this->next;
|
||||
kfree(this);
|
||||
|
|
|
@ -1209,6 +1209,18 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
|
|||
spin_unlock(&uncore->debug->lock);
|
||||
}
|
||||
|
||||
#define __vgpu_read(x) \
|
||||
static u##x \
|
||||
vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
|
||||
u##x val = __raw_uncore_read##x(uncore, reg); \
|
||||
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
|
||||
return val; \
|
||||
}
|
||||
__vgpu_read(8)
|
||||
__vgpu_read(16)
|
||||
__vgpu_read(32)
|
||||
__vgpu_read(64)
|
||||
|
||||
#define GEN2_READ_HEADER(x) \
|
||||
u##x val = 0; \
|
||||
assert_rpm_wakelock_held(uncore->rpm);
|
||||
|
@ -1414,6 +1426,16 @@ __gen_reg_write_funcs(gen8);
|
|||
#undef GEN6_WRITE_FOOTER
|
||||
#undef GEN6_WRITE_HEADER
|
||||
|
||||
#define __vgpu_write(x) \
|
||||
static void \
|
||||
vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
|
||||
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
|
||||
__raw_uncore_write##x(uncore, reg, val); \
|
||||
}
|
||||
__vgpu_write(8)
|
||||
__vgpu_write(16)
|
||||
__vgpu_write(32)
|
||||
|
||||
#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
|
||||
do { \
|
||||
(uncore)->funcs.mmio_writeb = x##_write8; \
|
||||
|
@ -1735,7 +1757,10 @@ static void uncore_raw_init(struct intel_uncore *uncore)
|
|||
{
|
||||
GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
|
||||
|
||||
if (IS_GEN(uncore->i915, 5)) {
|
||||
if (intel_vgpu_active(uncore->i915)) {
|
||||
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
|
||||
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
|
||||
} else if (IS_GEN(uncore->i915, 5)) {
|
||||
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
|
||||
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
|
||||
} else {
|
||||
|
|
Loading…
Add table
Reference in a new issue