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sparc64: Make %pil level 15 a pseudo-NMI.

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So that we can profile code even in a local_irq_disable() section,
only write 14 (instead of 15) into the %pil register to disable IRQs.

This allows PIL level 15 to serve as a pseudo NMI.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2008-11-23 21:55:29 -08:00
parent c6afec5e4d
commit b4f4372f96
12 changed files with 46 additions and 25 deletions
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9
arch/sparc/include/asm/pil.h
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@ -10,7 +10,12 @@
*
* In fact any XCALL which has to etrap/rtrap has a problem because
* it is difficult to prevent rtrap from running BH's, and that would
* need to be done if the XCALL arrived while %pil==15.
* need to be done if the XCALL arrived while %pil==PIL_NORMAL_MAX.
*
* Finally, in order to handle profiling events even when a
* local_irq_disable() is in progress, we only disable up to level 14
* interrupts. Profile counter overflow interrupts arrive at level
* 15.
*/
#define PIL_SMP_CALL_FUNC 1
#define PIL_SMP_RECEIVE_SIGNAL 2
@ -18,5 +23,7 @@
#define PIL_SMP_CTX_NEW_VERSION 4
#define PIL_DEVICE_IRQ 5
#define PIL_SMP_CALL_FUNC_SNGL 6
#define PIL_NORMAL_MAX 14
#define PIL_NMI 15
#endif /* !(_SPARC64_PIL_H) */