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drm/vc4: hvs: Fix frame count register readout
In order to get the field currently being output, the driver has been
using the display FIFO frame count in the HVS, reading a 6-bit field at
the offset 12 in the DISPSTATx register.
While that field is indeed at that location for the FIFO 1 and 2, the
one for the FIFO0 is actually in the DISPSTAT1 register, at the offset
18.
Fixes: e538092cb1
("drm/vc4: Enable precise vblank timestamping for interlaced modes.")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://lore.kernel.org/r/20220331143744.777652-3-maxime@cerno.tech
This commit is contained in:
parent
748acfc98a
commit
b51cd7ad14
4 changed files with 35 additions and 3 deletions
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@ -123,7 +123,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
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*vpos /= 2;
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*vpos /= 2;
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/* Use hpos to correct for field offset in interlaced mode. */
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/* Use hpos to correct for field offset in interlaced mode. */
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if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
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if (vc4_hvs_get_fifo_frame_count(dev, vc4_crtc_state->assigned_channel) % 2)
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*hpos += mode->crtc_htotal / 2;
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*hpos += mode->crtc_htotal / 2;
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}
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}
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@ -935,6 +935,7 @@ void vc4_irq_reset(struct drm_device *dev);
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extern struct platform_driver vc4_hvs_driver;
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extern struct platform_driver vc4_hvs_driver;
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void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
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void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
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int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
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int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
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u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo);
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int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
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int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
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@ -197,6 +197,29 @@ static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
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vc4_hvs_lut_load(crtc);
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vc4_hvs_lut_load(crtc);
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}
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}
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u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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u8 field = 0;
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switch (fifo) {
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case 0:
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field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
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SCALER_DISPSTAT1_FRCNT0);
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break;
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case 1:
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field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
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SCALER_DISPSTAT1_FRCNT1);
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break;
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case 2:
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field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
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SCALER_DISPSTAT2_FRCNT2);
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break;
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}
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return field;
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}
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int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
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int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
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{
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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@ -379,8 +379,6 @@
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# define SCALER_DISPSTATX_MODE_EOF 3
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# define SCALER_DISPSTATX_MODE_EOF 3
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# define SCALER_DISPSTATX_FULL BIT(29)
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# define SCALER_DISPSTATX_FULL BIT(29)
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# define SCALER_DISPSTATX_EMPTY BIT(28)
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# define SCALER_DISPSTATX_EMPTY BIT(28)
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# define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12)
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# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12
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# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
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# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
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# define SCALER_DISPSTATX_LINE_SHIFT 0
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# define SCALER_DISPSTATX_LINE_SHIFT 0
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@ -403,9 +401,15 @@
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(x) * (SCALER_DISPBKGND1 - \
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(x) * (SCALER_DISPBKGND1 - \
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SCALER_DISPBKGND0))
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SCALER_DISPBKGND0))
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#define SCALER_DISPSTAT1 0x00000058
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#define SCALER_DISPSTAT1 0x00000058
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# define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18)
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# define SCALER_DISPSTAT1_FRCNT0_SHIFT 18
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# define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12)
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# define SCALER_DISPSTAT1_FRCNT1_SHIFT 12
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#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
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#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
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(x) * (SCALER_DISPSTAT1 - \
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(x) * (SCALER_DISPSTAT1 - \
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SCALER_DISPSTAT0))
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SCALER_DISPSTAT0))
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#define SCALER_DISPBASE1 0x0000005c
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#define SCALER_DISPBASE1 0x0000005c
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#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
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#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
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(x) * (SCALER_DISPBASE1 - \
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(x) * (SCALER_DISPBASE1 - \
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@ -415,7 +419,11 @@
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(x) * (SCALER_DISPCTRL1 - \
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(x) * (SCALER_DISPCTRL1 - \
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SCALER_DISPCTRL0))
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SCALER_DISPCTRL0))
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#define SCALER_DISPBKGND2 0x00000064
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#define SCALER_DISPBKGND2 0x00000064
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#define SCALER_DISPSTAT2 0x00000068
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#define SCALER_DISPSTAT2 0x00000068
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# define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12)
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# define SCALER_DISPSTAT2_FRCNT2_SHIFT 12
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#define SCALER_DISPBASE2 0x0000006c
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#define SCALER_DISPBASE2 0x0000006c
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#define SCALER_DISPALPHA2 0x00000070
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#define SCALER_DISPALPHA2 0x00000070
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#define SCALER_GAMADDR 0x00000078
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#define SCALER_GAMADDR 0x00000078
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