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net: phy: bcm7xxx: enable EEE at the PHY level

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The 28nm Gigabit PHY on BCM7xxx chips comes out of reset with absolutely
no EEE capabilities, such that we would actually return that we do not
support EEE when accessing 3.20 (MDIO_PCS_EEE_ABLE) registers.

Poke through the vendor-specific C45 register to enable EEE globally at
the PHY level, and advertise supported EEE modes.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli 2014-08-22 18:55:45 -07:00 • committed by David S. Miller
parent a9f6309585
commit b8f9a02924
2 changed files with 34 additions and 0 deletions
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3
include/linux/brcmphy.h
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@ -214,5 +214,8 @@ static inline int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow,
MII_BCM54XX_SHD_DATA(val));
}
#define BRCM_CL45VEN_EEE_CONTROL 0x803d
#define LPI_FEATURE_EN 0x8000
#define LPI_FEATURE_EN_DIG1000X 0x4000
#endif /* _LINUX_BRCMPHY_H */