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PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields
[ Upstream commit 759574abd78e3b47ec45bbd31a64e8832cf73f97 ] Use FIELD_GET() to extract PCIe Negotiated Link Width field instead of custom masking and shifting. Similarly, change custom code that misleadingly used PCI_EXP_LNKSTA_NLW_SHIFT to prepare value for PCI_EXP_LNKCAP write to use FIELD_PREP() with correct field define (PCI_EXP_LNKCAP_MLW). Link: https://lore.kernel.org/r/20230919125648.1920-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 4 additions and 5 deletions
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@ -9,6 +9,7 @@
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* Author: Vidya Sagar <vidyas@nvidia.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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@ -346,8 +347,7 @@ static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
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*/
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val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
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if (val & PCI_EXP_LNKSTA_LBMS) {
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current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
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PCI_EXP_LNKSTA_NLW_SHIFT;
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current_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
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if (pcie->init_link_width > current_link_width) {
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dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
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val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
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@ -760,8 +760,7 @@ static void tegra_pcie_enable_system_interrupts(struct dw_pcie_rp *pp)
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val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
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PCI_EXP_LNKSTA);
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pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
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PCI_EXP_LNKSTA_NLW_SHIFT;
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pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w);
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val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
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PCI_EXP_LNKCTL);
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@ -920,7 +919,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
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/* Configure Max lane width from DT */
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val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
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val &= ~PCI_EXP_LNKCAP_MLW;
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val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
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val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes);
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dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
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/* Clear Slot Clock Configuration bit if SRNS configuration */
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