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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc

Browse source 
Pull sparc fixes from David Miller:

 1) Fix panics with SR-IOV, from Babu Moger.

 2) Wire up preadv2/pwritev2.

 3) Allow proper auto-loading of VIO devices, from John Paul Adrian
    Glaubitz.

 4) Recognize Sonoma cpus, from Khalid Aziz.

 5) Fix bootup regressions caused by syscall trace fixes made recently.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc64: Fix bootup regressions on some Kconfig combinations.
  sparc64: recognize and support Sonoma CPU type
  sparc: Implement and wire up vio_hotplug for vio.
  sparc: Implement and wire up modalias_show for vio.
  sparc/pci: Refactor dev_archdata initialization into pci_init_dev_archdata
  sparc/defconfigs: Remove CONFIG_IPV6_PRIVACY
  sparc: Write up preadv2/pwritev2 syscalls.
  sparc/PCI: Fix for panic while enabling SR-IOV
This commit is contained in:
Linus Torvalds 2016-05-02 09:32:50 -07:00
commit ba22906a9f
20 changed files with 119 additions and 68 deletions
Download patch file Download diff file Expand all files Collapse all files

1
arch/sparc/configs/sparc32_defconfig
View file

@ -24,7 +24,6 @@ CONFIG_INET_AH=y
CONFIG_INET_ESP=y CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y CONFIG_INET_IPCOMP=y
# CONFIG_INET_LRO is not set # CONFIG_INET_LRO is not set
CONFIG_IPV6_PRIVACY=y
CONFIG_INET6_AH=m CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m CONFIG_INET6_IPCOMP=m

1
arch/sparc/configs/sparc64_defconfig
View file

@ -48,7 +48,6 @@ CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=y CONFIG_INET_AH=y
CONFIG_INET_ESP=y CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y CONFIG_INET_IPCOMP=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_IPV6_OPTIMISTIC_DAD=y

1
arch/sparc/include/asm/spitfire.h
View file

@ -48,6 +48,7 @@
#define SUN4V_CHIP_SPARC_M6 0x06 #define SUN4V_CHIP_SPARC_M6 0x06
#define SUN4V_CHIP_SPARC_M7 0x07 #define SUN4V_CHIP_SPARC_M7 0x07
#define SUN4V_CHIP_SPARC64X 0x8a #define SUN4V_CHIP_SPARC64X 0x8a
#define SUN4V_CHIP_SPARC_SN 0x8b
#define SUN4V_CHIP_UNKNOWN 0xff #define SUN4V_CHIP_UNKNOWN 0xff
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__

4
arch/sparc/include/uapi/asm/unistd.h
View file

@ -423,8 +423,10 @@
#define __NR_setsockopt 355 #define __NR_setsockopt 355
#define __NR_mlock2 356 #define __NR_mlock2 356
#define __NR_copy_file_range 357 #define __NR_copy_file_range 357
#define __NR_preadv2 358
#define __NR_pwritev2 359
#define NR_syscalls 358 #define NR_syscalls 360
/* Bitmask values returned from kern_features system call. */ /* Bitmask values returned from kern_features system call. */
#define KERN_FEATURE_MIXED_MODE_STACK 0x00000001 #define KERN_FEATURE_MIXED_MODE_STACK 0x00000001

14
arch/sparc/kernel/cherrs.S
View file

@ -214,8 +214,7 @@ do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
subcc %g1, %g2, %g1 ! Next cacheline subcc %g1, %g2, %g1 ! Next cacheline
bge,pt %icc, 1b bge,pt %icc, 1b
nop nop
ba,pt %xcc, dcpe_icpe_tl1_common ba,a,pt %xcc, dcpe_icpe_tl1_common
nop
do_dcpe_tl1_fatal: do_dcpe_tl1_fatal:
sethi %hi(1f), %g7 sethi %hi(1f), %g7
@ -224,8 +223,7 @@ do_dcpe_tl1_fatal:
mov 0x2, %o0 mov 0x2, %o0
call cheetah_plus_parity_error call cheetah_plus_parity_error
add %sp, PTREGS_OFF, %o1 add %sp, PTREGS_OFF, %o1
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size do_dcpe_tl1,.-do_dcpe_tl1 .size do_dcpe_tl1,.-do_dcpe_tl1
.globl do_icpe_tl1 .globl do_icpe_tl1
@ -259,8 +257,7 @@ do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
subcc %g1, %g2, %g1 subcc %g1, %g2, %g1
bge,pt %icc, 1b bge,pt %icc, 1b
nop nop
ba,pt %xcc, dcpe_icpe_tl1_common ba,a,pt %xcc, dcpe_icpe_tl1_common
nop
do_icpe_tl1_fatal: do_icpe_tl1_fatal:
sethi %hi(1f), %g7 sethi %hi(1f), %g7
@ -269,8 +266,7 @@ do_icpe_tl1_fatal:
mov 0x3, %o0 mov 0x3, %o0
call cheetah_plus_parity_error call cheetah_plus_parity_error
add %sp, PTREGS_OFF, %o1 add %sp, PTREGS_OFF, %o1
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size do_icpe_tl1,.-do_icpe_tl1 .size do_icpe_tl1,.-do_icpe_tl1
.type dcpe_icpe_tl1_common,#function .type dcpe_icpe_tl1_common,#function
@ -456,7 +452,7 @@ __cheetah_log_error:
cmp %g2, 0x63 cmp %g2, 0x63
be c_cee be c_cee
nop nop
ba,pt %xcc, c_deferred ba,a,pt %xcc, c_deferred
.size __cheetah_log_error,.-__cheetah_log_error .size __cheetah_log_error,.-__cheetah_log_error
/* Cheetah FECC trap handling, we get here from tl{0,1}_fecc /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc

6
arch/sparc/kernel/cpu.c
View file

@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void)
sparc_pmu_type = "sparc-m7"; sparc_pmu_type = "sparc-m7";
break; break;
case SUN4V_CHIP_SPARC_SN:
sparc_cpu_type = "SPARC-SN";
sparc_fpu_type = "SPARC-SN integrated FPU";
sparc_pmu_type = "sparc-sn";
break;
case SUN4V_CHIP_SPARC64X: case SUN4V_CHIP_SPARC64X:
sparc_cpu_type = "SPARC64-X"; sparc_cpu_type = "SPARC64-X";
sparc_fpu_type = "SPARC64-X integrated FPU"; sparc_fpu_type = "SPARC64-X integrated FPU";

1
arch/sparc/kernel/cpumap.c
View file

@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
case SUN4V_CHIP_NIAGARA5: case SUN4V_CHIP_NIAGARA5:
case SUN4V_CHIP_SPARC_M6: case SUN4V_CHIP_SPARC_M6:
case SUN4V_CHIP_SPARC_M7: case SUN4V_CHIP_SPARC_M7:
case SUN4V_CHIP_SPARC_SN:
case SUN4V_CHIP_SPARC64X: case SUN4V_CHIP_SPARC64X:
rover_inc_table = niagara_iterate_method; rover_inc_table = niagara_iterate_method;
break; break;

11
arch/sparc/kernel/fpu_traps.S
View file

@ -100,8 +100,8 @@ do_fpdis:
fmuld %f0, %f2, %f26 fmuld %f0, %f2, %f26
faddd %f0, %f2, %f28 faddd %f0, %f2, %f28
fmuld %f0, %f2, %f30 fmuld %f0, %f2, %f30
b,pt %xcc, fpdis_exit ba,a,pt %xcc, fpdis_exit
nop
2: andcc %g5, FPRS_DU, %g0 2: andcc %g5, FPRS_DU, %g0
bne,pt %icc, 3f bne,pt %icc, 3f
fzero %f32 fzero %f32
@ -144,8 +144,8 @@ do_fpdis:
fmuld %f32, %f34, %f58 fmuld %f32, %f34, %f58
faddd %f32, %f34, %f60 faddd %f32, %f34, %f60
fmuld %f32, %f34, %f62 fmuld %f32, %f34, %f62
ba,pt %xcc, fpdis_exit ba,a,pt %xcc, fpdis_exit
nop
3: mov SECONDARY_CONTEXT, %g3 3: mov SECONDARY_CONTEXT, %g3
add %g6, TI_FPREGS, %g1 add %g6, TI_FPREGS, %g1
@ -197,8 +197,7 @@ fpdis_exit2:
fp_other_bounce: fp_other_bounce:
call do_fpother call do_fpother
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size fp_other_bounce,.-fp_other_bounce .size fp_other_bounce,.-fp_other_bounce
.align 32 .align 32

32
arch/sparc/kernel/head_64.S
View file

@ -414,6 +414,8 @@ sun4v_chip_type:
cmp %g2, 'T' cmp %g2, 'T'
be,pt %xcc, 70f be,pt %xcc, 70f
cmp %g2, 'M' cmp %g2, 'M'
be,pt %xcc, 70f
cmp %g2, 'S'
bne,pn %xcc, 49f bne,pn %xcc, 49f
nop nop
@ -433,6 +435,9 @@ sun4v_chip_type:
cmp %g2, '7' cmp %g2, '7'
be,pt %xcc, 5f be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M7, %g4 mov SUN4V_CHIP_SPARC_M7, %g4
cmp %g2, 'N'
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_SN, %g4
ba,pt %xcc, 49f ba,pt %xcc, 49f
nop nop
@ -461,9 +466,8 @@ sun4v_chip_type:
subcc %g3, 1, %g3 subcc %g3, 1, %g3
bne,pt %xcc, 41b bne,pt %xcc, 41b
add %g1, 1, %g1 add %g1, 1, %g1
mov SUN4V_CHIP_SPARC64X, %g4
ba,pt %xcc, 5f ba,pt %xcc, 5f
nop mov SUN4V_CHIP_SPARC64X, %g4
49: 49:
mov SUN4V_CHIP_UNKNOWN, %g4 mov SUN4V_CHIP_UNKNOWN, %g4
@ -548,8 +552,7 @@ sun4u_init:
stxa %g0, [%g7] ASI_DMMU stxa %g0, [%g7] ASI_DMMU
membar #Sync membar #Sync
ba,pt %xcc, sun4u_continue ba,a,pt %xcc, sun4u_continue
nop
sun4v_init: sun4v_init:
/* Set ctx 0 */ /* Set ctx 0 */
@ -560,14 +563,12 @@ sun4v_init:
mov SECONDARY_CONTEXT, %g7 mov SECONDARY_CONTEXT, %g7
stxa %g0, [%g7] ASI_MMU stxa %g0, [%g7] ASI_MMU
membar #Sync membar #Sync
ba,pt %xcc, niagara_tlb_fixup ba,a,pt %xcc, niagara_tlb_fixup
nop
sun4u_continue: sun4u_continue:
BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup) BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
ba,pt %xcc, spitfire_tlb_fixup ba,a,pt %xcc, spitfire_tlb_fixup
nop
niagara_tlb_fixup: niagara_tlb_fixup:
mov 3, %g2 /* Set TLB type to hypervisor. */ mov 3, %g2 /* Set TLB type to hypervisor. */
@ -595,6 +596,9 @@ niagara_tlb_fixup:
be,pt %xcc, niagara4_patch be,pt %xcc, niagara4_patch
nop nop
cmp %g1, SUN4V_CHIP_SPARC_M7 cmp %g1, SUN4V_CHIP_SPARC_M7
be,pt %xcc, niagara4_patch
nop
cmp %g1, SUN4V_CHIP_SPARC_SN
be,pt %xcc, niagara4_patch be,pt %xcc, niagara4_patch
nop nop
@ -639,8 +643,7 @@ niagara_patch:
call hypervisor_patch_cachetlbops call hypervisor_patch_cachetlbops
nop nop
ba,pt %xcc, tlb_fixup_done ba,a,pt %xcc, tlb_fixup_done
nop
cheetah_tlb_fixup: cheetah_tlb_fixup:
mov 2, %g2 /* Set TLB type to cheetah+. */ mov 2, %g2 /* Set TLB type to cheetah+. */
@ -659,8 +662,7 @@ cheetah_tlb_fixup:
call cheetah_patch_cachetlbops call cheetah_patch_cachetlbops
nop nop
ba,pt %xcc, tlb_fixup_done ba,a,pt %xcc, tlb_fixup_done
nop
spitfire_tlb_fixup: spitfire_tlb_fixup:
/* Set TLB type to spitfire. */ /* Set TLB type to spitfire. */
@ -774,8 +776,7 @@ setup_trap_table:
call %o1 call %o1
add %sp, (2047 + 128), %o0 add %sp, (2047 + 128), %o0
ba,pt %xcc, 2f ba,a,pt %xcc, 2f
nop
1: sethi %hi(sparc64_ttable_tl0), %o0 1: sethi %hi(sparc64_ttable_tl0), %o0
set prom_set_trap_table_name, %g2 set prom_set_trap_table_name, %g2
@ -814,8 +815,7 @@ setup_trap_table:
BRANCH_IF_ANY_CHEETAH(o2, o3, 1f) BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
ba,pt %xcc, 2f ba,a,pt %xcc, 2f
nop
/* Disable STICK_INT interrupts. */ /* Disable STICK_INT interrupts. */
1: 1:

12
arch/sparc/kernel/misctrap.S
View file

@ -18,8 +18,7 @@ __do_privact:
109: or %g7, %lo(109b), %g7 109: or %g7, %lo(109b), %g7
call do_privact call do_privact
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size __do_privact,.-__do_privact .size __do_privact,.-__do_privact
.type do_mna,#function .type do_mna,#function
@ -46,8 +45,7 @@ do_mna:
mov %l5, %o2 mov %l5, %o2
call mem_address_unaligned call mem_address_unaligned
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size do_mna,.-do_mna .size do_mna,.-do_mna
.type do_lddfmna,#function .type do_lddfmna,#function
@ -65,8 +63,7 @@ do_lddfmna:
mov %l5, %o2 mov %l5, %o2
call handle_lddfmna call handle_lddfmna
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size do_lddfmna,.-do_lddfmna .size do_lddfmna,.-do_lddfmna
.type do_stdfmna,#function .type do_stdfmna,#function
@ -84,8 +81,7 @@ do_stdfmna:
mov %l5, %o2 mov %l5, %o2
call handle_stdfmna call handle_stdfmna
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size do_stdfmna,.-do_stdfmna .size do_stdfmna,.-do_stdfmna
.type breakpoint_trap,#function .type breakpoint_trap,#function

42
arch/sparc/kernel/pci.c
View file

@ -245,6 +245,18 @@ static void pci_parse_of_addrs(struct platform_device *op,
} }
} }
static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
void *stc, void *host_controller,
struct platform_device *op,
int numa_node)
{
sd->iommu = iommu;
sd->stc = stc;
sd->host_controller = host_controller;
sd->op = op;
sd->numa_node = numa_node;
}
static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
struct device_node *node, struct device_node *node,
struct pci_bus *bus, int devfn) struct pci_bus *bus, int devfn)
@ -259,13 +271,10 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
if (!dev) if (!dev)
return NULL; return NULL;
op = of_find_device_by_node(node);
sd = &dev->dev.archdata; sd = &dev->dev.archdata;
sd->iommu = pbm->iommu; pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
sd->stc = &pbm->stc; pbm->numa_node);
sd->host_controller = pbm;
sd->op = op = of_find_device_by_node(node);
sd->numa_node = pbm->numa_node;
sd = &op->dev.archdata; sd = &op->dev.archdata;
sd->iommu = pbm->iommu; sd->iommu = pbm->iommu;
sd->stc = &pbm->stc; sd->stc = &pbm->stc;
@ -994,6 +1003,27 @@ void pcibios_set_master(struct pci_dev *dev)
/* No special bus mastering setup handling */ /* No special bus mastering setup handling */
} }
#ifdef CONFIG_PCI_IOV
int pcibios_add_device(struct pci_dev *dev)
{
struct pci_dev *pdev;
/* Add sriov arch specific initialization here.
* Copy dev_archdata from PF to VF
*/
if (dev->is_virtfn) {
struct dev_archdata *psd;
pdev = dev->physfn;
psd = &pdev->dev.archdata;
pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
psd->stc, psd->host_controller, NULL,
psd->numa_node);
}
return 0;
}
#endif /* CONFIG_PCI_IOV */
static int __init pcibios_init(void) static int __init pcibios_init(void)
{ {
pci_dfl_cache_line_size = 64 >> 2; pci_dfl_cache_line_size = 64 >> 2;

7
arch/sparc/kernel/setup_64.c
View file

@ -285,7 +285,8 @@ static void __init sun4v_patch(void)
sun4v_patch_2insn_range(&__sun4v_2insn_patch, sun4v_patch_2insn_range(&__sun4v_2insn_patch,
&__sun4v_2insn_patch_end); &__sun4v_2insn_patch_end);
if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7) if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN)
sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
&__sun_m7_2insn_patch_end); &__sun_m7_2insn_patch_end);
@ -524,6 +525,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type == SUN4V_CHIP_SPARC64X) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
cap |= HWCAP_SPARC_BLKINIT; cap |= HWCAP_SPARC_BLKINIT;
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
@ -532,6 +534,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type == SUN4V_CHIP_SPARC64X) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
cap |= HWCAP_SPARC_N2; cap |= HWCAP_SPARC_N2;
} }
@ -561,6 +564,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type == SUN4V_CHIP_SPARC64X) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
AV_SPARC_ASI_BLK_INIT | AV_SPARC_ASI_BLK_INIT |
@ -570,6 +574,7 @@ static void __init init_sparc64_elf_hwcap(void)
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
sun4v_chip_type == SUN4V_CHIP_SPARC64X) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
AV_SPARC_FMAF); AV_SPARC_FMAF);

18
arch/sparc/kernel/spiterrs.S
View file

@ -85,8 +85,7 @@ __spitfire_cee_trap_continue:
ba,pt %xcc, etraptl1 ba,pt %xcc, etraptl1
rd %pc, %g7 rd %pc, %g7
ba,pt %xcc, 2f ba,a,pt %xcc, 2f
nop
1: ba,pt %xcc, etrap_irq 1: ba,pt %xcc, etrap_irq
rd %pc, %g7 rd %pc, %g7
@ -100,8 +99,7 @@ __spitfire_cee_trap_continue:
mov %l5, %o2 mov %l5, %o2
call spitfire_access_error call spitfire_access_error
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size __spitfire_access_error,.-__spitfire_access_error .size __spitfire_access_error,.-__spitfire_access_error
/* This is the trap handler entry point for ECC correctable /* This is the trap handler entry point for ECC correctable
@ -179,8 +177,7 @@ __spitfire_data_access_exception_tl1:
mov %l5, %o2 mov %l5, %o2
call spitfire_data_access_exception_tl1 call spitfire_data_access_exception_tl1
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1 .size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
.type __spitfire_data_access_exception,#function .type __spitfire_data_access_exception,#function
@ -200,8 +197,7 @@ __spitfire_data_access_exception:
mov %l5, %o2 mov %l5, %o2
call spitfire_data_access_exception call spitfire_data_access_exception
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size __spitfire_data_access_exception,.-__spitfire_data_access_exception .size __spitfire_data_access_exception,.-__spitfire_data_access_exception
.type __spitfire_insn_access_exception_tl1,#function .type __spitfire_insn_access_exception_tl1,#function
@ -220,8 +216,7 @@ __spitfire_insn_access_exception_tl1:
mov %l5, %o2 mov %l5, %o2
call spitfire_insn_access_exception_tl1 call spitfire_insn_access_exception_tl1
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1 .size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
.type __spitfire_insn_access_exception,#function .type __spitfire_insn_access_exception,#function
@ -240,6 +235,5 @@ __spitfire_insn_access_exception:
mov %l5, %o2 mov %l5, %o2
call spitfire_insn_access_exception call spitfire_insn_access_exception
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
.size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception .size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception

2
arch/sparc/kernel/systbls_32.S
View file

@ -88,4 +88,4 @@ sys_call_table:
/*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr /*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
/*345*/ .long sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf /*345*/ .long sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
/*350*/ .long sys_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen /*350*/ .long sys_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen
/*355*/ .long sys_setsockopt, sys_mlock2, sys_copy_file_range /*355*/ .long sys_setsockopt, sys_mlock2, sys_copy_file_range, sys_preadv2, sys_pwritev2

4
arch/sparc/kernel/systbls_64.S
View file

@ -89,7 +89,7 @@ sys_call_table32:
/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr /*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
.word sys32_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf .word sys32_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
/*350*/ .word sys32_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen /*350*/ .word sys32_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen
.word compat_sys_setsockopt, sys_mlock2, sys_copy_file_range .word compat_sys_setsockopt, sys_mlock2, sys_copy_file_range, compat_sys_preadv2, compat_sys_pwritev2
#endif /* CONFIG_COMPAT */ #endif /* CONFIG_COMPAT */
@ -170,4 +170,4 @@ sys_call_table:
/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr /*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
.word sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf .word sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
/*350*/ .word sys64_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen /*350*/ .word sys64_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen
.word sys_setsockopt, sys_mlock2, sys_copy_file_range .word sys_setsockopt, sys_mlock2, sys_copy_file_range, sys_preadv2, sys_pwritev2

3
arch/sparc/kernel/utrap.S
View file

@ -11,8 +11,7 @@ utrap_trap: /* %g3=handler,%g4=level */
mov %l4, %o1 mov %l4, %o1
call bad_trap call bad_trap
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
invoke_utrap: invoke_utrap:
sllx %g3, 3, %g3 sllx %g3, 3, %g3

18
arch/sparc/kernel/vio.c
View file

@ -45,6 +45,14 @@ static const struct vio_device_id *vio_match_device(
return NULL; return NULL;
} }
static int vio_hotplug(struct device *dev, struct kobj_uevent_env *env)
{
const struct vio_dev *vio_dev = to_vio_dev(dev);
add_uevent_var(env, "MODALIAS=vio:T%sS%s", vio_dev->type, vio_dev->compat);
return 0;
}
static int vio_bus_match(struct device *dev, struct device_driver *drv) static int vio_bus_match(struct device *dev, struct device_driver *drv)
{ {
struct vio_dev *vio_dev = to_vio_dev(dev); struct vio_dev *vio_dev = to_vio_dev(dev);
@ -105,15 +113,25 @@ static ssize_t type_show(struct device *dev,
return sprintf(buf, "%s\n", vdev->type); return sprintf(buf, "%s\n", vdev->type);
} }
static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
const struct vio_dev *vdev = to_vio_dev(dev);
return sprintf(buf, "vio:T%sS%s\n", vdev->type, vdev->compat);
}
static struct device_attribute vio_dev_attrs[] = { static struct device_attribute vio_dev_attrs[] = {
__ATTR_RO(devspec), __ATTR_RO(devspec),
__ATTR_RO(type), __ATTR_RO(type),
__ATTR_RO(modalias),
__ATTR_NULL __ATTR_NULL
}; };
static struct bus_type vio_bus_type = { static struct bus_type vio_bus_type = {
.name = "vio", .name = "vio",
.dev_attrs = vio_dev_attrs, .dev_attrs = vio_dev_attrs,
.uevent = vio_hotplug,
.match = vio_bus_match, .match = vio_bus_match,
.probe = vio_device_probe, .probe = vio_device_probe,
.remove = vio_device_remove, .remove = vio_device_remove,

4
arch/sparc/kernel/vmlinux.lds.S
View file

@ -33,6 +33,10 @@ ENTRY(_start)
jiffies = jiffies_64; jiffies = jiffies_64;
#endif #endif
#ifdef CONFIG_SPARC64
ASSERT((swapper_tsb == 0x0000000000408000), "Error: sparc64 early assembler too large")
#endif
SECTIONS SECTIONS
{ {
#ifdef CONFIG_SPARC64 #ifdef CONFIG_SPARC64

3
arch/sparc/kernel/winfixup.S
View file

@ -32,8 +32,7 @@ fill_fixup:
rd %pc, %g7 rd %pc, %g7
call do_sparc64_fault call do_sparc64_fault
add %sp, PTREGS_OFF, %o0 add %sp, PTREGS_OFF, %o0
ba,pt %xcc, rtrap ba,a,pt %xcc, rtrap
nop
/* Be very careful about usage of the trap globals here. /* Be very careful about usage of the trap globals here.
* You cannot touch %g5 as that has the fault information. * You cannot touch %g5 as that has the fault information.

3
arch/sparc/mm/init_64.c
View file

@ -1769,6 +1769,7 @@ static void __init setup_page_offset(void)
max_phys_bits = 47; max_phys_bits = 47;
break; break;
case SUN4V_CHIP_SPARC_M7: case SUN4V_CHIP_SPARC_M7:
case SUN4V_CHIP_SPARC_SN:
default: default:
/* M7 and later support 52-bit virtual addresses. */ /* M7 and later support 52-bit virtual addresses. */
sparc64_va_hole_top = 0xfff8000000000000UL; sparc64_va_hole_top = 0xfff8000000000000UL;
@ -1986,6 +1987,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
*/ */
switch (sun4v_chip_type) { switch (sun4v_chip_type) {
case SUN4V_CHIP_SPARC_M7: case SUN4V_CHIP_SPARC_M7:
case SUN4V_CHIP_SPARC_SN:
pagecv_flag = 0x00; pagecv_flag = 0x00;
break; break;
default: default:
@ -2138,6 +2140,7 @@ void __init paging_init(void)
*/ */
switch (sun4v_chip_type) { switch (sun4v_chip_type) {
case SUN4V_CHIP_SPARC_M7: case SUN4V_CHIP_SPARC_M7:
case SUN4V_CHIP_SPARC_SN:
page_cache4v_flag = _PAGE_CP_4V; page_cache4v_flag = _PAGE_CP_4V;
break; break;
default: default: