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https://github.com/Fishwaldo/Star64_linux.git
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ASoC: starfive: Add TDM dai driver for SOF
in sof arch, the host linux dai driver sets clock and reset. the control of audio params is handled in dsp side. Signed-off-by: carter.li <carter.li@starfivetech.com>
This commit is contained in:
carter.li
parent
294085b095
commit
bc526cda61
3 changed files with 430 additions and 0 deletions
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@ -68,3 +68,12 @@ config SND_SOC_STARFIVE_SPDIF_PCM
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help
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Say Y or N if you want to add a custom ALSA extension that registers
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a PCM and uses PIO to transfer data.
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config SND_SOC_STARFIVE_SOF_TDM_DAI
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tristate "Generic STARFIVE TDM DAI support for Sound Open Firmware"
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depends on HAVE_CLK && SND_SOC_STARFIVE
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help
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Say Y if you want to enable generic STARFIVE TDM DAI support to be used
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with Sound Open Firmware. This module takes care of enabling
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clocks, pinctrl for TDM DAIs. The rest of DAI
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control is taken care of by SOF firmware.
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@ -11,3 +11,4 @@ spdif-y := starfive_spdif.o
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spdif-$(CONFIG_SND_SOC_STARFIVE_SPDIF_PCM) += starfive_spdif_pcm.o
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obj-$(CONFIG_SND_SOC_STARFIVE_I2S) += starfive_i2s.o
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obj-$(CONFIG_SND_SOC_STARFIVE_SOF_TDM_DAI) += starfive_sof_dai.o
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420
sound/soc/starfive/starfive_sof_dai.c
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420
sound/soc/starfive/starfive_sof_dai.c
Normal file
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@ -0,0 +1,420 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* TDM driver for the StarFive JH7110 SoC
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*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/reset.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <linux/dma/starfive-dma.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#define TDM_PCMGBCR 0x00
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#define PCMGBCR_ENABLE BIT(0)
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#define CLKPOL_BIT 5
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#define ELM_BIT 3
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#define SYNCM_BIT 2
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#define MS_BIT 1
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#define TDM_PCMTXCR 0x04
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#define PCMTXCR_TXEN BIT(0)
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#define IFL_BIT 11
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#define WL_BIT 8
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#define SSCALE_BIT 4
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#define SL_BIT 2
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#define LRJ_BIT 1
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#define TDM_PCMRXCR 0x08
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#define PCMRXCR_RXEN BIT(0)
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#define TDM_PCMDIV 0x0c
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enum TDM_MASTER_SLAVE_MODE {
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TDM_AS_MASTER = 0,
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TDM_AS_SLAVE,
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};
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enum TDM_CLKPOL {
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/* tx raising and rx falling */
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TDM_TX_RASING_RX_FALLING = 0,
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/* tx falling and rx raising */
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TDM_TX_FALLING_RX_RASING,
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};
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enum TDM_ELM {
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/* only work while SYNCM=0 */
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TDM_ELM_LATE = 0,
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TDM_ELM_EARLY,
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};
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enum TDM_SYNCM {
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/* short frame sync */
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TDM_SYNCM_SHORT = 0,
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/* long frame sync */
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TDM_SYNCM_LONG,
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};
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enum TDM_IFL {
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/* FIFO to send or received : half-1/2, Quarter-1/4 */
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TDM_FIFO_HALF = 0,
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TDM_FIFO_QUARTER,
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};
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enum TDM_WL {
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/* send or received word length */
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TDM_8BIT_WORD_LEN = 0,
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TDM_16BIT_WORD_LEN,
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TDM_20BIT_WORD_LEN,
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TDM_24BIT_WORD_LEN,
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TDM_32BIT_WORD_LEN,
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};
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enum TDM_SL {
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/* send or received slot length */
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TDM_8BIT_SLOT_LEN = 0,
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TDM_16BIT_SLOT_LEN,
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TDM_32BIT_SLOT_LEN,
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};
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enum TDM_LRJ {
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/* left-justify or right-justify */
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TDM_RIGHT_JUSTIFY = 0,
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TDM_LEFT_JUSTIFT,
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};
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struct tdm_chan_cfg {
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enum TDM_IFL ifl;
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enum TDM_WL wl;
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unsigned char sscale;
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enum TDM_SL sl;
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enum TDM_LRJ lrj;
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unsigned char enable;
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};
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struct jh7110_tdm_dev {
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void __iomem *tdm_base;
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struct device *dev;
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struct clk_bulk_data clks[6];
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struct reset_control *resets;
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enum TDM_CLKPOL clkpolity;
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enum TDM_ELM elm;
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enum TDM_SYNCM syncm;
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enum TDM_MASTER_SLAVE_MODE ms_mode;
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struct tdm_chan_cfg tx;
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struct tdm_chan_cfg rx;
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u16 syncdiv;
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u32 samplerate;
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u32 pcmclk;
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u32 saved_pcmgbcr;
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u32 saved_pcmtxcr;
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u32 saved_pcmrxcr;
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u32 saved_pcmdiv;
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};
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static inline u32 jh7110_tdm_readl(struct jh7110_tdm_dev *dev, u16 reg)
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{
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return readl_relaxed(dev->tdm_base + reg);
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}
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static inline void jh7110_tdm_writel(struct jh7110_tdm_dev *dev, u16 reg, u32 val)
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{
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writel_relaxed(val, dev->tdm_base + reg);
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}
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static void jh7110_tdm_clk_disable(struct jh7110_tdm_dev *priv)
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{
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clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);
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}
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static int jh7110_tdm_clk_enable(struct jh7110_tdm_dev *priv)
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{
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int ret;
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clks), priv->clks);
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if (ret) {
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dev_err(priv->dev, "Failed to enable tdm clocks\n");
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return ret;
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}
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ret = reset_control_deassert(priv->resets);
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if (ret) {
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dev_err(priv->dev, "%s: failed to deassert tdm resets\n", __func__);
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goto dis_tdm_clk;
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}
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/* select tdm_ext clock as the clock source for tdm */
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ret = clk_set_parent(priv->clks[5].clk, priv->clks[4].clk);
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if (ret) {
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dev_err(priv->dev, "Can't set extern clock source for clk_tdm\n");
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goto dis_tdm_clk;
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}
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return 0;
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dis_tdm_clk:
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clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);
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return ret;
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}
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#ifdef CONFIG_PM
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static int jh7110_tdm_runtime_suspend(struct device *dev)
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{
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struct jh7110_tdm_dev *priv = dev_get_drvdata(dev);
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jh7110_tdm_clk_disable(priv);
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return 0;
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}
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static int jh7110_tdm_runtime_resume(struct device *dev)
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{
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struct jh7110_tdm_dev *priv = dev_get_drvdata(dev);
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return jh7110_tdm_clk_enable(priv);
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}
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#endif
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/*
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* To stop dma first, we must implement this function, because it is
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* called before stopping the stream.
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*/
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static const struct snd_soc_component_driver jh7110_tdm_component = {
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.name = "jh7110-tdm",
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};
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static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct jh7110_tdm_dev *dev = snd_soc_dai_get_drvdata(dai);
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int chan_wl, chan_sl, chan_nr;
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unsigned int data_width;
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unsigned int mclk_rate;
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unsigned int dma_bus_width;
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int channels;
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int ret;
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struct snd_dmaengine_dai_dma_data *dma_data = NULL;
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dev_dbg(dev->dev, "tdm: jh7110_tdm_hw_params");
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channels = params_channels(params);
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data_width = params_width(params);
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dev->samplerate = params_rate(params);
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switch (dev->samplerate) {
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/* There are some limitation when using 8k sample rate */
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case 8000:
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mclk_rate = 12288000;
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if ((data_width == 16) || (channels == 1)) {
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pr_err("TDM: not support 16bit or 1-channel when using 8k sample rate\n");
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return -EINVAL;
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}
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break;
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case 11025:
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/* sysclk */
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mclk_rate = 11289600;
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break;
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case 16000:
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mclk_rate = 12288000;
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break;
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case 22050:
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mclk_rate = 11289600;
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break;
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case 32000:
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mclk_rate = 12288000;
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break;
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case 44100:
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mclk_rate = 11289600;
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break;
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case 48000:
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mclk_rate = 12288000;
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break;
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default:
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pr_err("TDM: not support sample rate:%d\n", dev->samplerate);
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return -EINVAL;
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}
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dev->pcmclk = channels * dev->samplerate * data_width;
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ret = clk_set_rate(dev->clks[0].clk, mclk_rate);
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if (ret) {
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dev_err(dev->dev, "Can't set clk_mclk: %d\n", ret);
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return ret;
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}
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ret = clk_set_rate(dev->clks[3].clk, dev->pcmclk);
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if (ret) {
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dev_err(dev->dev, "Can't set clk_tdm_internal: %d\n", ret);
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return ret;
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}
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ret = clk_set_parent(dev->clks[5].clk, dev->clks[4].clk);
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if (ret) {
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dev_err(dev->dev, "Can't set clock source for clk_tdm: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(dev->clks[1].clk);
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if (ret) {
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dev_err(dev->dev, "Failed to prepare enable clk_tdm_ahb\n");
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return ret;
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}
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ret = clk_prepare_enable(dev->clks[2].clk);
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if (ret) {
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dev_err(dev->dev, "Failed to prepare enable clk_tdm_apb\n");
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return ret;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops jh7110_tdm_dai_ops = {
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.hw_params = jh7110_tdm_hw_params
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};
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static int jh7110_tdm_dai_probe(struct snd_soc_dai *dai)
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{
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struct jh7110_tdm_dev *dev = snd_soc_dai_get_drvdata(dai);
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// snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
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snd_soc_dai_set_drvdata(dai, dev);
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return 0;
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}
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#define JH7110_TDM_RATES SNDRV_PCM_RATE_8000_48000
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#define JH7110_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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static struct snd_soc_dai_driver jh7110_tdm_dai = {
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.name = "ssp0",
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.id = 0,
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.playback = {
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.channels_min = 1,
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.channels_max = 8,
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.rates = JH7110_TDM_RATES,
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.formats = JH7110_TDM_FORMATS,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 8,
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.rates = JH7110_TDM_RATES,
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.formats = JH7110_TDM_FORMATS,
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},
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.ops = &jh7110_tdm_dai_ops,
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.probe = jh7110_tdm_dai_probe,
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.symmetric_rate = 1,
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};
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static int jh7110_tdm_clk_reset_init(struct platform_device *pdev, struct jh7110_tdm_dev *dev)
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{
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int ret;
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dev->clks[0].id = "mclk_inner";
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dev->clks[1].id = "clk_tdm_ahb";
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dev->clks[2].id = "clk_tdm_apb";
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dev->clks[3].id = "clk_tdm_internal";
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dev->clks[4].id = "clk_tdm_ext";
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dev->clks[5].id = "clk_tdm";
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ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(dev->clks), dev->clks);
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if (ret) {
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dev_err(&pdev->dev, "failed to get tdm clocks\n");
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goto exit;
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}
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dev->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
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if (IS_ERR(dev->resets)) {
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ret = PTR_ERR(dev->resets);
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dev_err(&pdev->dev, "Failed to get tdm resets");
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goto exit;
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}
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ret = jh7110_tdm_clk_enable(dev);
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exit:
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return ret;
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}
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static int jh7110_tdm_probe(struct platform_device *pdev)
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{
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struct jh7110_tdm_dev *dev;
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struct resource *res;
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int ret;
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dev_dbg(&pdev->dev, "jh7110_tdm_probe\n");
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dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dev->tdm_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dev->tdm_base))
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return PTR_ERR(dev->tdm_base);
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dev->dev = &pdev->dev;
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ret = jh7110_tdm_clk_reset_init(pdev, dev);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable audio-tdm clock\n");
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return ret;
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}
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dev_set_drvdata(&pdev->dev, dev);
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ret = devm_snd_soc_register_component(&pdev->dev, &jh7110_tdm_component,
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&jh7110_tdm_dai, 1);
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if (ret != 0) {
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dev_err(&pdev->dev, "failed to register dai\n");
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return ret;
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}
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pm_runtime_enable(&pdev->dev);
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return 0;
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}
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static int jh7110_tdm_dev_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct of_device_id jh7110_tdm_of_match[] = {
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{.compatible = "starfive,jh7110-sof-dai",},
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{}
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};
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MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match);
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static const struct dev_pm_ops jh7110_tdm_pm_ops = {
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SET_RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend,
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jh7110_tdm_runtime_resume, NULL)
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};
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static struct platform_driver jh7110_tdm_driver = {
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.driver = {
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.name = "jh7110-sof-tdm",
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.of_match_table = jh7110_tdm_of_match,
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.pm = &jh7110_tdm_pm_ops,
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},
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.probe = jh7110_tdm_probe,
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.remove = jh7110_tdm_dev_remove,
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};
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module_platform_driver(jh7110_tdm_driver);
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MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
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MODULE_DESCRIPTION("Starfive TDM Controller Driver");
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MODULE_LICENSE("GPL v2");
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