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https://github.com/Fishwaldo/Star64_linux.git
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Merge branch 'queue/irq/gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into devel
This commit is contained in:
commit
bcae888039
18 changed files with 55 additions and 65 deletions
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@ -65,11 +65,11 @@ static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
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return ptr;
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}
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static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
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static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g;
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g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
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g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
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return g;
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}
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@ -287,7 +287,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
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static void gpio_irq_disable(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(d);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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writel_relaxed(mask, &g->clr_falling);
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@ -296,7 +296,7 @@ static void gpio_irq_disable(struct irq_data *d)
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static void gpio_irq_enable(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(d);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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unsigned status = irqd_get_trigger_type(d);
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@ -327,8 +327,9 @@ static struct irq_chip gpio_irqchip = {
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};
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
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{
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unsigned int irq = irq_desc_get_irq(desc);
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struct davinci_gpio_regs __iomem *g;
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u32 mask = 0xffff;
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struct davinci_gpio_controller *d;
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@ -396,7 +397,7 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
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struct davinci_gpio_regs __iomem *g;
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u32 mask;
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d = (struct davinci_gpio_controller *)data->handler_data;
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d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
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g = (struct davinci_gpio_regs __iomem *)d->regs;
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mask = __gpio_mask(data->irq - d->gpio_irq);
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@ -578,15 +579,13 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
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writel_relaxed(~0, &g->clr_falling);
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writel_relaxed(~0, &g->clr_rising);
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/* set up all irqs in this bank */
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irq_set_chained_handler(bank_irq, gpio_irq_handler);
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/*
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* Each chip handles 32 gpios, and each irq bank consists of 16
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* gpio irqs. Pass the irq bank's corresponding controller to
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* the chained irq handler.
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*/
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irq_set_handler_data(bank_irq, &chips[gpio / 32]);
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irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
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&chips[gpio / 32]);
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binten |= BIT(bank);
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}
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