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drm/i915: Disable trickle feed in ironlake_init_clock_gating()

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We disable trickle feed in all the (relevant) clock gating functions,
except ironlake_init_clock_gating(). Copy paste the same code there as
well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-06-07 10:47:03 +03:00 • committed by Daniel Vetter
parent 20f949670f
commit bdad2b2f31
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/i915/intel_pm.c
View file

@ -4391,6 +4391,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
int pipe;
/* Required for FBC */ /* Required for FBC */
dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
@ -4450,6 +4451,13 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
I915_WRITE(CACHE_MODE_0, I915_WRITE(CACHE_MODE_0,
_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
for_each_pipe(pipe) {
I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) |
DISPPLANE_TRICKLE_FEED_DISABLE);
intel_flush_display_plane(dev_priv, pipe);
}
ibx_init_clock_gating(dev); ibx_init_clock_gating(dev);
} }