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net/mlx5: QCAM register firmware command support

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The QCAM register provides capability bit for all the QoS registers
using ACCESS_REG command.

Signed-off-by: Huy Nguyen <huyn@mellanox.com>
Reviewed-by: Parav Pandit <parav@mellanox.com>
Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Huy Nguyen 2017-07-18 16:03:17 -05:00 • committed by Saeed Mahameed
parent ee20598194
commit c02762eb20
6 changed files with 79 additions and 1 deletions
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14
include/linux/mlx5/device.h
View file

@ -1000,6 +1000,14 @@ enum mlx5_mcam_feature_groups {
MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
};
enum mlx5_qcam_reg_groups {
MLX5_QCAM_REGS_FIRST_128 = 0x0,
};
enum mlx5_qcam_feature_groups {
MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
};
/* GET Dev Caps macros */
#define MLX5_CAP_GEN(mdev, cap) \
MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
@ -1108,6 +1116,12 @@ enum mlx5_mcam_feature_groups {
#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
#define MLX5_CAP_QCAM_REG(mdev, fld) \
MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
#define MLX5_CAP_FPGA(mdev, cap) \
MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)

2
include/linux/mlx5/driver.h
View file

@ -109,6 +109,7 @@ enum {
enum {
MLX5_REG_QETCR = 0x4005,
MLX5_REG_QTCT = 0x400a,
MLX5_REG_QCAM = 0x4019,
MLX5_REG_DCBX_PARAM = 0x4020,
MLX5_REG_DCBX_APP = 0x4021,
MLX5_REG_FPGA_CAP = 0x4022,
@ -798,6 +799,7 @@ struct mlx5_core_dev {
u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
} caps;
phys_addr_t iseg_base;
struct mlx5_init_seg __iomem *iseg;

40
include/linux/mlx5/mlx5_ifc.h
View file

@ -838,7 +838,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 cc_modify_allowed[0x1];
u8 start_pad[0x1];
u8 cache_line_128byte[0x1];
u8 reserved_at_165[0xb];
u8 reserved_at_165[0xa];
u8 qcam_reg[0x1];
u8 gid_table_size[0x10];
u8 out_of_seq_cnt[0x1];
@ -7890,6 +7891,43 @@ struct mlx5_ifc_mcam_reg_bits {
u8 reserved_at_1c0[0x80];
};
struct mlx5_ifc_qcam_access_reg_cap_mask {
u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
u8 qpdpm[0x1];
u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
u8 qdpm[0x1];
u8 qpts[0x1];
u8 qcap[0x1];
u8 qcam_access_reg_cap_mask_0[0x1];
};
struct mlx5_ifc_qcam_qos_feature_cap_mask {
u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
u8 qpts_trust_both[0x1];
};
struct mlx5_ifc_qcam_reg_bits {
u8 reserved_at_0[0x8];
u8 feature_group[0x8];
u8 reserved_at_10[0x8];
u8 access_reg_group[0x8];
u8 reserved_at_20[0x20];
union {
struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
u8 reserved_at_0[0x80];
} qos_access_reg_cap_mask;
u8 reserved_at_c0[0x80];
union {
struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
u8 reserved_at_0[0x80];
} qos_feature_cap_mask;
u8 reserved_at_1c0[0x80];
};
struct mlx5_ifc_pcap_reg_bits {
u8 reserved_at_0[0x8];
u8 local_port[0x8];