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powerpc: Make single-stepping emulation (mostly) usable on 32-bit

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The sc instruction emulation can't be done the same way on 32-bit
as 64-bit yet, but this should work OK.

Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Paul Mackerras 2005-10-28 22:48:08 +10:00
parent d73e0c99f5
commit c032524f0d
3 changed files with 28 additions and 1 deletions
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17
arch/powerpc/lib/sstep.c
View file

@ -10,13 +10,18 @@
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/ptrace.h> #include <linux/ptrace.h>
#include <linux/config.h>
#include <asm/sstep.h> #include <asm/sstep.h>
#include <asm/processor.h> #include <asm/processor.h>
extern char system_call_common[]; extern char system_call_common[];
#ifdef CONFIG_PPC64
/* Bits in SRR1 that are copied from MSR */ /* Bits in SRR1 that are copied from MSR */
#define MSR_MASK 0xffffffff87c0ffff #define MSR_MASK 0xffffffff87c0ffff
#else
#define MSR_MASK 0x87c0ffff
#endif
/* /*
* Determine whether a conditional branch instruction would branch. * Determine whether a conditional branch instruction would branch.
@ -66,6 +71,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
if (branch_taken(instr, regs)) if (branch_taken(instr, regs))
regs->nip = imm; regs->nip = imm;
return 1; return 1;
#ifdef CONFIG_PPC64
case 17: /* sc */ case 17: /* sc */
/* /*
* N.B. this uses knowledge about how the syscall * N.B. this uses knowledge about how the syscall
@ -79,6 +85,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
regs->nip = (unsigned long) &system_call_common; regs->nip = (unsigned long) &system_call_common;
regs->msr = MSR_KERNEL; regs->msr = MSR_KERNEL;
return 1; return 1;
#endif
case 18: /* b */ case 18: /* b */
imm = instr & 0x03fffffc; imm = instr & 0x03fffffc;
if (imm & 0x02000000) if (imm & 0x02000000)
@ -121,6 +128,15 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
if ((regs->msr & MSR_SF) == 0) if ((regs->msr & MSR_SF) == 0)
regs->nip &= 0xffffffffUL; regs->nip &= 0xffffffffUL;
return 1; return 1;
case 0x124: /* mtmsr */
imm = regs->gpr[rd];
if ((imm & MSR_RI) == 0)
/* can't step mtmsr that would clear MSR_RI */
return -1;
regs->msr = imm;
regs->nip += 4;
return 1;
#ifdef CONFIG_PPC64
case 0x164: /* mtmsrd */ case 0x164: /* mtmsrd */
/* only MSR_EE and MSR_RI get changed if bit 15 set */ /* only MSR_EE and MSR_RI get changed if bit 15 set */
/* mtmsrd doesn't change MSR_HV and MSR_ME */ /* mtmsrd doesn't change MSR_HV and MSR_ME */
@ -135,6 +151,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
if ((imm & MSR_SF) == 0) if ((imm & MSR_SF) == 0)
regs->nip &= 0xffffffffUL; regs->nip &= 0xffffffffUL;
return 1; return 1;
#endif
} }
} }
return 0; return 0;

8
include/asm-powerpc/reg.h
View file

@ -51,9 +51,17 @@
#define __MASK(X) (1UL<<(X)) #define __MASK(X) (1UL<<(X))
#endif #endif
#ifdef CONFIG_PPC64
#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
#else
/* so tests for these bits fail on 32-bit */
#define MSR_SF 0
#define MSR_ISF 0
#define MSR_HV 0
#endif
#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */

4
include/asm-ppc64/sstep.h → include/asm-powerpc/sstep.h
View file

@ -16,8 +16,10 @@ struct pt_regs;
* we don't allow putting a breakpoint on an mtmsrd instruction. * we don't allow putting a breakpoint on an mtmsrd instruction.
* Similarly we don't allow breakpoints on rfid instructions. * Similarly we don't allow breakpoints on rfid instructions.
* These macros tell us if an instruction is a mtmsrd or rfid. * These macros tell us if an instruction is a mtmsrd or rfid.
* Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
* and an mtmsrd (64-bit).
*/ */
#define IS_MTMSRD(instr) (((instr) & 0xfc0007fe) == 0x7c000164) #define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024) #define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
/* Emulate instructions that cause a transfer of control. */ /* Emulate instructions that cause a transfer of control. */