GitHub-Mirror/Star64_linux
2
0
Fork 0
mirror of https://github.com/Fishwaldo/Star64_linux.git synced 2025-04-16 03:14:09 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

serial: sh-sci: Add SCIFA/B SCPCR register definitions

Browse source 
Add the register definitions for the Serial Port Control and Data
Registers on SCIFA/SCIFB, which are needed for RTS/CTS pin control.

Extracted from patches by Magnus Damm <damm+renesas@opensource.se>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Geert Uytterhoeven 2015-04-30 18:21:27 +02:00 • committed by Greg Kroah-Hartman
parent 76735e9d55
commit c097abc33f
2 changed files with 32 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
drivers/tty/serial/sh-sci.c
View file

@ -168,6 +168,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid,
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -188,6 +190,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid,
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -207,6 +211,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid,
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = { 0x30, 16 },
[SCPDR] = { 0x34, 16 },
}, },
/* /*
@ -226,6 +232,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid,
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = { 0x30, 16 },
[SCPDR] = { 0x34, 16 },
}, },
/* /*
@ -246,6 +254,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = { 0x20, 16 }, [SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 }, [SCLSR] = { 0x24, 16 },
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -265,6 +275,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid,
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -284,6 +296,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = { 0x20, 16 }, [SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 }, [SCLSR] = { 0x24, 16 },
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -303,6 +317,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = { 0x20, 16 }, [SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 }, [SCLSR] = { 0x24, 16 },
[HSSRR] = { 0x40, 16 }, [HSSRR] = { 0x40, 16 },
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -323,6 +339,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = { 0x24, 16 }, [SCLSR] = { 0x24, 16 },
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -343,6 +361,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = { 0x24, 16 }, [SCSPTR] = { 0x24, 16 },
[SCLSR] = { 0x28, 16 }, [SCLSR] = { 0x28, 16 },
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
/* /*
@ -363,6 +383,8 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCSPTR] = sci_reg_invalid, [SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid, [SCLSR] = sci_reg_invalid,
[HSSRR] = sci_reg_invalid, [HSSRR] = sci_reg_invalid,
[SCPCR] = sci_reg_invalid,
[SCPDR] = sci_reg_invalid,
}, },
}; };

10
drivers/tty/serial/sh-sci.h
View file

@ -24,6 +24,8 @@ enum {
SCRFDR, /* Receive FIFO Data Count Register */ SCRFDR, /* Receive FIFO Data Count Register */
SCSPTR, /* Serial Port Register */ SCSPTR, /* Serial Port Register */
HSSRR, /* Sampling Rate Register */ HSSRR, /* Sampling Rate Register */
SCPCR, /* Serial Port Control Register */
SCPDR, /* Serial Port Data Register */
SCIx_NR_REGS, SCIx_NR_REGS,
}; };
@ -79,6 +81,14 @@ enum {
/* HSSRR HSCIF */ /* HSSRR HSCIF */
#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */ #define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
#define SCPCR_RTSC (1 << 4) /* Serial Port RTS Pin / Output Pin */
#define SCPCR_CTSC (1 << 3) /* Serial Port CTS Pin / Input Pin */
/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
#define SCPDR_RTSD (1 << 4) /* Serial Port RTS Output Pin Data */
#define SCPDR_CTSD (1 << 3) /* Serial Port CTS Input Pin Data */
#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)