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net: dsa: microchip: ksz8795: move cpu_select_interface to extra function

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This patch moves the cpu interface selection code to a individual
function specific for ksz8795. It will make it simpler to customize the
code path for different switches supported by this driver.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Grzeschik 2021-04-27 09:09:02 +02:00 • committed by David S. Miller
parent 4b5baca040
commit c2ac4d2ac5
1 changed files with 50 additions and 42 deletions
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92
drivers/net/dsa/microchip/ksz8795.c
View file

@ -909,10 +909,58 @@ static void ksz8_port_mirror_del(struct dsa_switch *ds, int port,
PORT_MIRROR_SNIFFER, false); PORT_MIRROR_SNIFFER, false);
} }
static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
{
struct ksz_port *p = &dev->ports[port];
u8 data8;
if (!p->interface && dev->compat_interface) {
dev_warn(dev->dev,
"Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
"Please update your device tree.\n",
port);
p->interface = dev->compat_interface;
}
/* Configure MII interface for proper network communication. */
ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
data8 &= ~PORT_INTERFACE_TYPE;
data8 &= ~PORT_GMII_1GPS_MODE;
switch (p->interface) {
case PHY_INTERFACE_MODE_MII:
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_RMII:
data8 |= PORT_INTERFACE_RMII;
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_GMII:
data8 |= PORT_GMII_1GPS_MODE;
data8 |= PORT_INTERFACE_GMII;
p->phydev.speed = SPEED_1000;
break;
default:
data8 &= ~PORT_RGMII_ID_IN_ENABLE;
data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
data8 |= PORT_RGMII_ID_IN_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
data8 |= PORT_RGMII_ID_OUT_ENABLE;
data8 |= PORT_GMII_1GPS_MODE;
data8 |= PORT_INTERFACE_RGMII;
p->phydev.speed = SPEED_1000;
break;
}
ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
p->phydev.duplex = 1;
}
static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
{ {
struct ksz_port *p = &dev->ports[port]; struct ksz_port *p = &dev->ports[port];
u8 data8, member; u8 member;
/* enable broadcast storm limit */ /* enable broadcast storm limit */
ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
@ -929,47 +977,7 @@ static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
if (cpu_port) { if (cpu_port) {
if (!p->interface && dev->compat_interface) { ksz8795_cpu_interface_select(dev, port);
dev_warn(dev->dev,
"Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
"Please update your device tree.\n",
port);
p->interface = dev->compat_interface;
}
/* Configure MII interface for proper network communication. */
ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
data8 &= ~PORT_INTERFACE_TYPE;
data8 &= ~PORT_GMII_1GPS_MODE;
switch (p->interface) {
case PHY_INTERFACE_MODE_MII:
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_RMII:
data8 |= PORT_INTERFACE_RMII;
p->phydev.speed = SPEED_100;
break;
case PHY_INTERFACE_MODE_GMII:
data8 |= PORT_GMII_1GPS_MODE;
data8 |= PORT_INTERFACE_GMII;
p->phydev.speed = SPEED_1000;
break;
default:
data8 &= ~PORT_RGMII_ID_IN_ENABLE;
data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
data8 |= PORT_RGMII_ID_IN_ENABLE;
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
data8 |= PORT_RGMII_ID_OUT_ENABLE;
data8 |= PORT_GMII_1GPS_MODE;
data8 |= PORT_INTERFACE_RGMII;
p->phydev.speed = SPEED_1000;
break;
}
ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
p->phydev.duplex = 1;
member = dev->port_mask; member = dev->port_mask;
} else { } else {