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IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMs

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Previously, the GIC accessors were only accessing u32 registers but
newer CMs may actually be 64-bit on MIPS64 cores. As a result of which,
extended these accessors to support 64-bit reads and writes.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras 2015-07-14 10:26:09 +01:00 • committed by Ralf Baechle
parent 3885c2b463
commit c3f57f02e3
2 changed files with 84 additions and 47 deletions
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10
include/linux/irqchip/mips-gic.h
View file

@ -45,8 +45,14 @@
#define GIC_SH_REVISIONID_OFS 0x0020
/* Convert an interrupt number to a byte offset/bit for multi-word registers */
#define GIC_INTR_OFS(intr) (((intr) / 32) * 4)
#define GIC_INTR_BIT(intr) ((intr) % 32)
#define GIC_INTR_OFS(intr) ({ \
unsigned bits = mips_cm_is64 ? 64 : 32; \
unsigned reg_idx = (intr) / bits; \
unsigned reg_width = bits / 8; \
\
reg_idx * reg_width; \
})
#define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32))
/* Polarity : Reset Value is always 0 */
#define GIC_SH_SET_POLARITY_OFS 0x0100