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arm64: dts: imx8mq: properly describe IRQ hierarchy
The GPCv2 sits between most of the peripherals and the GIC and functions as a wakeup controller for the CPU cores. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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1 changed files with 4 additions and 2 deletions
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@ -11,8 +11,7 @@
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#include "imx8mq-pinfunc.h"
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#include "imx8mq-pinfunc.h"
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/ {
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/ {
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/* This should really be the GPC, but we need a driver for this first */
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interrupt-parent = <&gpc>;
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <2>;
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@ -257,6 +256,9 @@
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gpc: gpc@303a0000 {
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gpc: gpc@303a0000 {
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compatible = "fsl,imx8mq-gpc";
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compatible = "fsl,imx8mq-gpc";
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reg = <0x303a0000 0x10000>;
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reg = <0x303a0000 0x10000>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <3>;
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pgc {
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pgc {
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#address-cells = <1>;
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#address-cells = <1>;
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