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MIPS: Add support for XPA.
Add support for extended physical addressing (XPA) so that 32-bit platforms can access equal to or greater than 40 bits of physical addresses. NOTE: 1) XPA and EVA are not the same and cannot be used simultaneously. 2) If you configure your kernel for XPA, the PTEs and all address sizes become 64-bit. 3) Your platform MUST have working HIGHMEM support. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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11 changed files with 173 additions and 44 deletions
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@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp)
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
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#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
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static inline pte_t
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pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
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pte.pte_low = pgprot_val(prot);
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pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
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(pgprot_val(prot) & ~_PFNX_MASK);
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pte.pte_high = (pfn << _PFN_SHIFT) |
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(pgprot_val(prot) & ~_PFN_MASK);
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return pte;
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}
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@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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/* Swap entries must have VALID and GLOBAL bits cleared. */
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#define __swp_type(x) (((x).val >> 2) & 0x1f)
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#define __swp_offset(x) ((x).val >> 7)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
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#define __swp_type(x) (((x).val >> 4) & 0x1f)
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#define __swp_offset(x) ((x).val >> 9)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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