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drm/amdgpu: define the TMZ bit for the PTE

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Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
This commit is contained in:
Alex Deucher 2019-08-07 22:31:50 -05:00
parent e90c2b210b
commit c5efd80f48
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
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@ -54,6 +54,9 @@ struct amdgpu_bo_list_entry;
#define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SYSTEM (1ULL << 1)
#define AMDGPU_PTE_SNOOPED (1ULL << 2) #define AMDGPU_PTE_SNOOPED (1ULL << 2)
/* RV+ */
#define AMDGPU_PTE_TMZ (1ULL << 3)
/* VI only */ /* VI only */
#define AMDGPU_PTE_EXECUTABLE (1ULL << 4) #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)