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arm64: dts: mt8195: Add Ethernet controller
Add Ethernet controller node for mt8195. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Biao Huang <biao.huang@mediatek.com> Link: https://lore.kernel.org/r/20230105010712.10116-3-biao.huang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -78,6 +78,23 @@
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};
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};
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ð {
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phy-mode ="rgmii-id";
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phy-handle = <ðernet_phy0>;
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snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
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snps,reset-delays-us = <0 10000 80000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <ð_default_pins>;
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pinctrl-1 = <ð_sleep_pins>;
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status = "okay";
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mdio {
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ethernet_phy0: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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};
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&i2c6 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c6_pins>;
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@ -258,6 +275,66 @@
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};
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&pio {
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eth_default_pins: eth-default-pins {
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pins-txd {
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pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
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<PINMUX_GPIO78__FUNC_GBE_TXD2>,
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<PINMUX_GPIO79__FUNC_GBE_TXD1>,
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<PINMUX_GPIO80__FUNC_GBE_TXD0>;
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drive-strength = <MTK_DRIVE_8mA>;
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};
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pins-cc {
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pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
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<PINMUX_GPIO88__FUNC_GBE_TXEN>,
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<PINMUX_GPIO87__FUNC_GBE_RXDV>,
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<PINMUX_GPIO86__FUNC_GBE_RXC>;
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drive-strength = <MTK_DRIVE_8mA>;
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};
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pins-rxd {
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pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
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<PINMUX_GPIO82__FUNC_GBE_RXD2>,
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<PINMUX_GPIO83__FUNC_GBE_RXD1>,
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<PINMUX_GPIO84__FUNC_GBE_RXD0>;
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};
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pins-mdio {
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pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
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<PINMUX_GPIO90__FUNC_GBE_MDIO>;
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input-enable;
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};
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pins-power {
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pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
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<PINMUX_GPIO92__FUNC_GPIO92>;
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output-high;
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};
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};
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eth_sleep_pins: eth-sleep-pins {
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pins-txd {
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pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
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<PINMUX_GPIO78__FUNC_GPIO78>,
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<PINMUX_GPIO79__FUNC_GPIO79>,
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<PINMUX_GPIO80__FUNC_GPIO80>;
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};
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pins-cc {
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pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
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<PINMUX_GPIO88__FUNC_GPIO88>,
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<PINMUX_GPIO87__FUNC_GPIO87>,
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<PINMUX_GPIO86__FUNC_GPIO86>;
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};
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pins-rxd {
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pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
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<PINMUX_GPIO82__FUNC_GPIO82>,
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<PINMUX_GPIO83__FUNC_GPIO83>,
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<PINMUX_GPIO84__FUNC_GPIO84>;
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};
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pins-mdio {
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pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
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<PINMUX_GPIO90__FUNC_GPIO90>;
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input-disable;
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bias-disable;
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};
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};
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gpio_keys_pins: gpio-keys-pins {
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pins {
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pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
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@ -1113,6 +1113,98 @@
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status = "disabled";
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};
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eth: ethernet@11021000 {
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compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
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reg = <0 0x11021000 0 0x4000>;
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interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "macirq";
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clock-names = "axi",
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"apb",
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"mac_main",
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"ptp_ref",
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"rmii_internal",
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"mac_cg";
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clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
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<&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
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<&topckgen CLK_TOP_SNPS_ETH_250M>,
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<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
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<&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
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<&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
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assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
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<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
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<&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
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assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
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<&topckgen CLK_TOP_ETHPLL_D8>,
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<&topckgen CLK_TOP_ETHPLL_D10>;
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power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
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mediatek,pericfg = <&infracfg_ao>;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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snps,txpbl = <16>;
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snps,rxpbl = <16>;
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snps,clk-csr = <0>;
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status = "disabled";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <0x7>;
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snps,rd_osr_lmt = <0x7>;
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snps,blen = <0 0 0 0 16 8 4>;
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x0>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x0>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x0>;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <4>;
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snps,tx-sched-wrr;
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queue0 {
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snps,weight = <0x10>;
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snps,dcb-algorithm;
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snps,priority = <0x0>;
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};
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queue1 {
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snps,weight = <0x11>;
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue2 {
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snps,weight = <0x12>;
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue3 {
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snps,weight = <0x13>;
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snps,dcb-algorithm;
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snps,priority = <0x3>;
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};
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};
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};
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xhci0: usb@11200000 {
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compatible = "mediatek,mt8195-xhci",
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"mediatek,mtk-xhci";
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