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net: stmmac: Configure gtxclk based on speed
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31764b3dcd
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1 changed files with 47 additions and 0 deletions
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@ -16,6 +16,50 @@
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#include "stmmac.h"
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#include "stmmac_platform.h"
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/*
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* GMAC_GTXCLK 为 gmac 的时钟分频寄存器,低8位为分频值
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* bit name access default descript
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* [31] clk_gmac_gtxclk enable RW 0x0 "1:enable; 0:disable"
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* [30] reserved - 0x0 reserved
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* [29:8] reserved - 0x0 reserved
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* [7:0] clk_gmac_gtxclk divide ratio RW 0x4 divide value
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*
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* gmac 的 root 时钟为500M, gtxclk 需求的时钟如下:
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* 1000M: gtxclk为125M,分频值为500/125 = 0x4
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* 100M: gtxclk为25M, 分频值为500/25 = 0x14
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* 10M: gtxclk为2.5M,分频值为500/2.5 = 0xc8
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*/
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#ifdef CONFIG_SOC_STARFIVE_VIC7100
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#define CLKGEN_BASE 0x11800000
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#define CLKGEN_GMAC_GTXCLK_OFFSET 0x1EC
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#define CLKGEN_GMAC_GTXCLK_ADDR (CLKGEN_BASE + CLKGEN_GMAC_GTXCLK_OFFSET)
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#define CLKGEN_125M_DIV 0x4
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#define CLKGEN_25M_DIV 0x14
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#define CLKGEN_2_5M_DIV 0xc8
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static void dwmac_fixed_speed(void *priv, unsigned int speed)
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{
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u32 value;
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void *addr = ioremap(CLKGEN_GMAC_GTXCLK_ADDR, sizeof(value));
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if (!addr) {
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pr_err("%s can't remap CLKGEN_GMAC_GTXCLK_ADDR\n", __func__);
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return;
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}
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value = readl(addr) & (~0x000000FF);
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switch (speed) {
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case SPEED_1000: value |= CLKGEN_125M_DIV; break;
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case SPEED_100: value |= CLKGEN_25M_DIV; break;
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case SPEED_10: value |= CLKGEN_2_5M_DIV; break;
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default: iounmap(addr); return;
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}
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writel(value, addr); /*set gmac gtxclk*/
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iounmap(addr);
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}
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#endif
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static int dwmac_generic_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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@ -52,6 +96,9 @@ static int dwmac_generic_probe(struct platform_device *pdev)
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if (ret)
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goto err_remove_config_dt;
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}
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#ifdef CONFIG_SOC_STARFIVE_VIC7100
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plat_dat->fix_mac_speed = dwmac_fixed_speed;
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#endif
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (ret)
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