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powerpc/rcpm: add RCPM driver

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There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.

The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[scottwood: remove __KERNEL__ ifdef]
Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
chenhui zhao 2015-11-20 17:13:59 +08:00 • committed by Scott Wood
parent e7affb1dba
commit d17799f9c1
9 changed files with 571 additions and 0 deletions
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105
include/linux/fsl/guts.h
View file

@ -189,4 +189,109 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
#endif
struct ccsr_rcpm_v1 {
u8 res0000[4];
__be32 cdozsr; /* 0x0004 Core Doze Status Register */
u8 res0008[4];
__be32 cdozcr; /* 0x000c Core Doze Control Register */
u8 res0010[4];
__be32 cnapsr; /* 0x0014 Core Nap Status Register */
u8 res0018[4];
__be32 cnapcr; /* 0x001c Core Nap Control Register */
u8 res0020[4];
__be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
u8 res0028[4];
__be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
u8 res0030[4];
__be32 cwaitsr; /* 0x0034 Core Wait Status Register */
u8 res0038[4];
__be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
__be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
#define RCPM_POWMGTCSR_SLP 0x00020000
u8 res0044[12];
__be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
u8 res0054[16];
__be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
u8 res0068[4];
__be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
u8 res0070[4];
__be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
u8 res0078[4];
__be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
u8 res0080[4];
__be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
u8 res0088[4];
__be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
u8 res0090[4];
__be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
u8 res0098[4];
__be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
};
struct ccsr_rcpm_v2 {
u8 res_00[12];
__be32 tph10sr0; /* Thread PH10 Status Register */
u8 res_10[12];
__be32 tph10setr0; /* Thread PH10 Set Control Register */
u8 res_20[12];
__be32 tph10clrr0; /* Thread PH10 Clear Control Register */
u8 res_30[12];
__be32 tph10psr0; /* Thread PH10 Previous Status Register */
u8 res_40[12];
__be32 twaitsr0; /* Thread Wait Status Register */
u8 res_50[96];
__be32 pcph15sr; /* Physical Core PH15 Status Register */
__be32 pcph15setr; /* Physical Core PH15 Set Control Register */
__be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
__be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
u8 res_c0[16];
__be32 pcph20sr; /* Physical Core PH20 Status Register */
__be32 pcph20setr; /* Physical Core PH20 Set Control Register */
__be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
__be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
__be32 pcpw20sr; /* Physical Core PW20 Status Register */
u8 res_e0[12];
__be32 pcph30sr; /* Physical Core PH30 Status Register */
__be32 pcph30setr; /* Physical Core PH30 Set Control Register */
__be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
__be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
u8 res_100[32];
__be32 ippwrgatecr; /* IP Power Gating Control Register */
u8 res_124[12];
__be32 powmgtcsr; /* Power Management Control & Status Reg */
#define RCPM_POWMGTCSR_LPM20_RQ 0x00100000
#define RCPM_POWMGTCSR_LPM20_ST 0x00000200
#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
u8 res_134[12];
__be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
u8 res_150[12];
__be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
u8 res_160[12];
__be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
u8 res_170[12];
__be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
u8 res_180[12];
__be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
u8 res_190[12];
__be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
__be32 pctbenr; /* Physical Core Time Base Enable Reg */
__be32 pctbclkselr; /* Physical Core Time Base Clock Select */
__be32 tbclkdivr; /* Time Base Clock Divider Register */
u8 res_1ac[4];
__be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
__be32 clpcl10sr; /* Cluster PCL10 Status Register */
__be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
__be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
__be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
__be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
__be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
__be32 cdpwroksetr; /* Core Domain Power OK Set Register */
__be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
__be32 cdpwrensr; /* Core Domain Power Enable Status Register */
__be32 cddslsr; /* Core Domain Deep Sleep Status Register */
u8 res_1e8[8];
__be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
u8 res_300[3568];
};
#endif