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ARM: dove: use fixed PCI i/o mapping

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The i/o regions are changed from 1MB to 64KB. It's likely that the 2nd
bus is not setup correctly.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring 2012-02-28 16:05:10 -06:00
parent 8ef6e6201b
commit d191bb6961
5 changed files with 17 additions and 64 deletions
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1
arch/arm/Kconfig
View file

@ -537,7 +537,6 @@ config ARCH_DOVE
select PCI select PCI
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION select PLAT_ORION
help help
Support for the Marvell Dove SoC 88AP510 Support for the Marvell Dove SoC 88AP510

10
arch/arm/mach-dove/common.c
View file

@ -49,16 +49,6 @@ static struct map_desc dove_io_desc[] __initdata = {
.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
.length = DOVE_NB_REGS_SIZE, .length = DOVE_NB_REGS_SIZE,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = DOVE_PCIE0_IO_VIRT_BASE,
.pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
.length = DOVE_PCIE0_IO_SIZE,
.type = MT_DEVICE,
}, {
.virtual = DOVE_PCIE1_IO_VIRT_BASE,
.pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
.length = DOVE_PCIE1_IO_SIZE,
.type = MT_DEVICE,
}, },
}; };

8
arch/arm/mach-dove/include/mach/dove.h
View file

@ -50,14 +50,12 @@
#define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_NB_REGS_SIZE SZ_8M
#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000
#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 #define DOVE_PCIE0_IO_BUS_BASE 0x00000000
#define DOVE_PCIE0_IO_SIZE SZ_1M #define DOVE_PCIE0_IO_SIZE SZ_64K
#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 #define DOVE_PCIE1_IO_BUS_BASE 0x00010000
#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 #define DOVE_PCIE1_IO_SIZE SZ_64K
#define DOVE_PCIE1_IO_SIZE SZ_1M
/* /*
* Dove Core Registers Map * Dove Core Registers Map

19
arch/arm/mach-dove/include/mach/io.h
View file

@ -1,19 +0,0 @@
/*
* arch/arm/mach-dove/include/mach/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "dove.h"
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
DOVE_PCIE0_IO_VIRT_BASE))
#endif

43
arch/arm/mach-dove/pcie.c
View file

@ -26,9 +26,8 @@ struct pcie_port {
u8 root_bus_nr; u8 root_bus_nr;
void __iomem *base; void __iomem *base;
spinlock_t conf_lock; spinlock_t conf_lock;
char io_space_name[16];
char mem_space_name[16]; char mem_space_name[16];
struct resource res[2]; struct resource res;
}; };
static struct pcie_port pcie_port[2]; static struct pcie_port pcie_port[2];
@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
orion_pcie_setup(pp->base); orion_pcie_setup(pp->base);
/* if (pp->index == 0)
* IORESOURCE_IO pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
*/ else
snprintf(pp->io_space_name, sizeof(pp->io_space_name), pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
"PCIe %d I/O", pp->index);
pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
pp->res[0].name = pp->io_space_name;
if (pp->index == 0) {
pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
} else {
pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
}
pp->res[0].flags = IORESOURCE_IO;
if (request_resource(&ioport_resource, &pp->res[0]))
panic("Request PCIe IO resource failed\n");
pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
/* /*
* IORESOURCE_MEM * IORESOURCE_MEM
@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d MEM", pp->index); "PCIe %d MEM", pp->index);
pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
pp->res[1].name = pp->mem_space_name; pp->res.name = pp->mem_space_name;
if (pp->index == 0) { if (pp->index == 0) {
pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
} else { } else {
pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
} }
pp->res[1].flags = IORESOURCE_MEM; pp->res.flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &pp->res[1])) if (request_resource(&iomem_resource, &pp->res))
panic("Request PCIe Memory resource failed\n"); panic("Request PCIe Memory resource failed\n");
pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
return 1; return 1;
} }
@ -210,7 +195,7 @@ static void __init add_pcie_port(int index, unsigned long base)
pp->root_bus_nr = -1; pp->root_bus_nr = -1;
pp->base = (void __iomem *)base; pp->base = (void __iomem *)base;
spin_lock_init(&pp->conf_lock); spin_lock_init(&pp->conf_lock);
memset(pp->res, 0, sizeof(pp->res)); memset(&pp->res, 0, sizeof(pp->res));
} else { } else {
printk(KERN_INFO "link down, ignoring\n"); printk(KERN_INFO "link down, ignoring\n");
} }