SPI changes for v3.8

Primarily SPI device driver bug fixes, one removal of an old driver, and
 some new tegra support. There is some core code change too, but all in
 all pretty small stuff. The new features to note are:
 - Common code for describing GPIO CS lines in the device tree
 - Remove the SPI_BUFSIZ limitation on spi_write_the_read()
 - core spi ensures bits_per_word is set correctly
 - SPARC can now use SPI
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Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6

Pull SPI updates from Grant Likely:
 "Primarily SPI device driver bug fixes, one removal of an old driver,
  and some new tegra support.  There is some core code change too, but
  all in all pretty small stuff.

  The new features to note are:
   - Common code for describing GPIO CS lines in the device tree
   - Remove the SPI_BUFSIZ limitation on spi_write_the_read()
   - core spi ensures bits_per_word is set correctly
   - SPARC can now use SPI"

* tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6: (36 commits)
  spi/sparc: Allow of_register_spi_devices for sparc
  spi: Remove HOTPLUG section attributes
  spi: Add support for specifying 3-wire mode via device tree
  spi: Fix comparison of different integer types
  spi/orion: Add SPI_CHPA and SPI_CPOL support to kirkwood driver.
  spi/sh: Add SH Mobile series as dependency to MSIOF controller
  spi/sh-msiof: Remove unneeded clock name
  spi: Remove SPI_BUFSIZ restriction on spi_write_then_read()
  spi/stmp: remove obsolete driver
  spi/clps711x: New SPI master driver
  spi: omap2-mcspi: remove duplicate inclusion of linux/err.h
  spi: omap2-mcspi: Fix the redifine warning
  spi/sh-hspi: add CS manual control support
  of_spi: add generic binding support to specify cs gpio
  spi: omap2-mcspi: remove duplicated include from spi-omap2-mcspi.c
  spi/bitbang: (cosmetic) simplify list manipulation
  spi/bitbang: avoid needless loop flow manipulations
  spi/omap: fix D0/D1 direction confusion
  spi: tegra: add spi driver for sflash controller
  spi: Dont call master->setup if not populated
  ...

Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt

@@ -0,0 +1,26 @@
+NVIDIA Tegra20 SFLASH controller.
+
+Required properties:
+- compatible : should be "nvidia,tegra20-sflash".
+- reg: Should contain SFLASH registers location and length.
+- interrupts: Should contain SFLASH interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this SFLASH controller.
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+spi@7000d600 {
+	compatible = "nvidia,tegra20-sflash";
+	reg = <0x7000c380 0x80>;
+	interrupts = <0 39 0x04>;
+	nvidia,dma-request-selector = <&apbdma 16>;
+	spi-max-frequency = <25000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+};
+

Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt

@@ -0,0 +1,26 @@
+NVIDIA Tegra20/Tegra30 SLINK controller.
+
+Required properties:
+- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
+- reg: Should contain SLINK registers location and length.
+- interrupts: Should contain SLINK interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this SLINK controller.
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+slink@7000d600 {
+	compatible = "nvidia,tegra20-slink";
+	reg = <0x7000d600 0x200>;
+	interrupts = <0 82 0x04>;
+	nvidia,dma-request-selector = <&apbdma 16>;
+	spi-max-frequency = <25000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+};
+

Documentation/devicetree/bindings/spi/omap-spi.txt

@@ -6,7 +6,9 @@ Required properties:
   - "ti,omap4-spi" for OMAP4+.
 - ti,spi-num-cs : Number of chipselect supported  by the instance.
 - ti,hwmods: Name of the hwmod associated to the McSPI
-
+- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
+			  input. The default is D0 as input and
+			  D1 as output.
 
 Example:
 

Documentation/devicetree/bindings/spi/spi-bus.txt

@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
     		recommended practice.
+- cs-gpios	  - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -24,6 +25,22 @@ support describing the chip select layout.
 Optional property:
 - num-cs : total number of chipselects
 
+If cs-gpios is used the number of chip select will automatically increased
+with max(cs-gpios > hw cs)
+
+So if for example the controller has 2 CS lines, and the cs-gpios
+property looks like this:
+
+cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
+
+Then it should be configured so that num_chipselect = 4 with the
+following mapping:
+
+cs0 : &gpio1 0 0
+cs1 : native
+cs2 : &gpio1 1 0
+cs3 : &gpio1 2 0
+
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -36,6 +53,11 @@ contain the following properties.
     		shifted clock phase (CPHA) mode
 - spi-cs-high     - (optional) Empty property indicating device requires
     		chip select active high
+- spi-3wire       - (optional) Empty property indicating device requires
+    		    3-wire mode.
+
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the cs_gpio
 
 SPI example for an MPC5200 SPI bus:
 	spi@f00 {