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riscv/starfive: Add VIC7100 support
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@ -10,6 +10,72 @@ config SOC_SIFIVE
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help
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This enables support for SiFive SoC platform hardware.
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config SOC_STARFIVE_VIC7100
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bool "StarFive VIC7100 SoC"
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select SOC_SIFIVE
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select OF_RESERVED_MEM
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select SIFIVE_L2
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select SIFIVE_L2_FLUSH
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select DW_AXI_DMAC_STARFIVE
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select GPIO_STARFIVE_VIC
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select HW_RANDOM_STARFIVE_VIC
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help
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This enables support for StarFive VIC7100 SoC Platform Hardware.
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menu "StarFive VIC7100 SoC Debug Option"
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depends on SOC_STARFIVE_VIC7100
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choice
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prompt "VIC7100 SOC GMAC Speed"
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depends on SOC_STARFIVE_VIC7100
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default FPGA_GMAC_SPEED_AUTO
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help
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choice VIC7100 GMAC speed.
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(GMAC only works well on 10M/duple, for FPGA board.)
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config FPGA_GMAC_SPEED10
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bool "GMAC works on 10M mode"
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config FPGA_GMAC_SPEED100
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bool "GMAC works on 100M mode"
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config FPGA_GMAC_SPEED_AUTO
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bool "GMAC works on auto mode"
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endchoice
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config FPGA_GMAC_FLUSH_DDR
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bool "VIC7100 SOC GMAC description and packet buffer flush"
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depends on SOC_STARFIVE_VIC7100
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depends on STMMAC_ETH
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default y if SOC_STARFIVE_VIC7100
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help
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enable VIC7100 GMAC description and packet buffer flush
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config MMC_DW_FLUSH_DDR
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bool "VIC7100 SOC DW MMC buffer flush"
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depends on SOC_STARFIVE_VIC7100
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depends on MMC_DW
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default y if SOC_STARFIVE_VIC7100
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help
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enable VIC7100 DW MMC description and data buffer flush
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config USB_CDNS3_HOST_FLUSH_DMA
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bool "Cadence USB3 host controller flush dma memery"
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depends on USB
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depends on USB_CDNS3
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depends on SOC_STARFIVE_VIC7100
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default y if SOC_STARFIVE_VIC7100
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help
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enable VIC7100 DW USB CDNS3 driver data buffer flush
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config SOC_STARFIVE_VIC7100_I2C_GPIO
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bool "VIC7100 SOC I2C GPIO init"
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depends on I2C_DESIGNWARE_CORE
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depends on SOC_STARFIVE_VIC7100
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default y if SOC_STARFIVE_VIC7100
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help
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enable VIC7100 DW I2C GPIO init in Synopsys DesignWare master driver
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endmenu
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config SOC_VIRT
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bool "QEMU Virt Machine"
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select CLINT_TIMER if RISCV_M_MODE
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36
include/soc/starfive/vic7100.h
Normal file
36
include/soc/starfive/vic7100.h
Normal file
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@ -0,0 +1,36 @@
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#ifndef STARFIVE_VIC7100_H
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#define STARFIVE_VIC7100_H
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#include <asm/io.h>
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#include <soc/sifive/sifive_l2_cache.h>
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/*cache.c*/
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#define starfive_flush_dcache(start, len) \
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sifive_l2_flush64_range(start, len)
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/*dma*/
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#define CONFIG_DW_DEBUG
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#define DMA_PRINTK(fmt,...) \
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printk("[DW_DMA] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
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#ifdef CONFIG_DW_DEBUG
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#define DMA_DEBUG(fmt,...) \
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printk("[DW_DMA_DEBUG] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
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#else
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#define DMA_BEBUG(fmt,...)
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#endif
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#define _dw_virt_to_phys(vaddr) (pfn_to_phys(virt_to_pfn(vaddr)))
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#define _dw_phys_to_virt(paddr) (page_to_virt(phys_to_page(paddr)))
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void *dw_phys_to_virt(u64 phys);
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u64 dw_virt_to_phys(void *vaddr);
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int dw_dma_async_do_memcpy(void *src, void *dst, size_t size);
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int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size);
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int dw_dma_memcpy(void *src, void *dst, size_t size);
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int dw_dma_mem2mem_arry(void);
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int dw_dma_mem2mem_test(void);
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#endif /*STARFIVE_VIC7100_H*/
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