riscv/starfive: Add VIC7100 support

arch/riscv/Kconfig.socs

@@ -10,6 +10,72 @@ config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config SOC_STARFIVE_VIC7100
+	bool "StarFive VIC7100 SoC"
+	select SOC_SIFIVE
+	select OF_RESERVED_MEM
+	select SIFIVE_L2
+	select SIFIVE_L2_FLUSH
+	select DW_AXI_DMAC_STARFIVE
+	select GPIO_STARFIVE_VIC
+	select HW_RANDOM_STARFIVE_VIC
+	help
+	  This enables support for StarFive VIC7100 SoC Platform Hardware.
+
+menu "StarFive VIC7100 SoC Debug Option"
+	depends on SOC_STARFIVE_VIC7100
+
+choice
+	prompt "VIC7100 SOC GMAC Speed"
+	depends on SOC_STARFIVE_VIC7100
+	default FPGA_GMAC_SPEED_AUTO
+	help
+	  choice VIC7100 GMAC speed.
+	  (GMAC only works well on 10M/duple, for FPGA board.)
+
+	config FPGA_GMAC_SPEED10
+		bool "GMAC works on 10M mode"
+	config FPGA_GMAC_SPEED100
+		bool "GMAC works on 100M mode"
+	config FPGA_GMAC_SPEED_AUTO
+		bool "GMAC works on auto mode"
+endchoice
+
+config FPGA_GMAC_FLUSH_DDR
+	bool "VIC7100 SOC GMAC description and packet buffer flush"
+	depends on SOC_STARFIVE_VIC7100
+	depends on STMMAC_ETH
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 GMAC description and packet buffer flush
+
+config MMC_DW_FLUSH_DDR
+	bool "VIC7100 SOC DW MMC buffer flush"
+	depends on SOC_STARFIVE_VIC7100
+	depends on MMC_DW
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 DW MMC description and data buffer flush
+
+config USB_CDNS3_HOST_FLUSH_DMA
+	bool "Cadence USB3 host controller flush dma memery"
+	depends on USB
+	depends on USB_CDNS3
+	depends on SOC_STARFIVE_VIC7100
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 DW USB CDNS3 driver data buffer flush
+
+config SOC_STARFIVE_VIC7100_I2C_GPIO
+	bool "VIC7100 SOC I2C GPIO init"
+	depends on I2C_DESIGNWARE_CORE
+	depends on SOC_STARFIVE_VIC7100
+	default y if SOC_STARFIVE_VIC7100
+	help
+	  enable VIC7100 DW I2C GPIO init in Synopsys DesignWare master driver
+
+endmenu
+
 config SOC_VIRT
 	bool "QEMU Virt Machine"
 	select CLINT_TIMER if RISCV_M_MODE

include/soc/starfive/vic7100.h

@@ -0,0 +1,36 @@
+#ifndef STARFIVE_VIC7100_H
+#define STARFIVE_VIC7100_H
+#include <asm/io.h>
+#include <soc/sifive/sifive_l2_cache.h>
+
+/*cache.c*/
+#define starfive_flush_dcache(start, len) \
+	sifive_l2_flush64_range(start, len)
+
+/*dma*/
+#define CONFIG_DW_DEBUG
+
+#define DMA_PRINTK(fmt,...) \
+	printk("[DW_DMA] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
+
+#ifdef CONFIG_DW_DEBUG
+#define DMA_DEBUG(fmt,...) \
+	printk("[DW_DMA_DEBUG] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
+#else
+#define DMA_BEBUG(fmt,...)
+#endif
+
+#define _dw_virt_to_phys(vaddr) (pfn_to_phys(virt_to_pfn(vaddr)))
+#define _dw_phys_to_virt(paddr) (page_to_virt(phys_to_page(paddr)))
+
+void *dw_phys_to_virt(u64 phys);
+u64 dw_virt_to_phys(void *vaddr);
+
+int dw_dma_async_do_memcpy(void *src, void *dst, size_t size);
+int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size);
+int dw_dma_memcpy(void *src, void *dst, size_t size);
+
+int dw_dma_mem2mem_arry(void);
+int dw_dma_mem2mem_test(void);
+
+#endif /*STARFIVE_VIC7100_H*/